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Patent

Switched-Capacitor Charge Pumps

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TLDR
In this article, a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the transistors are described.
Abstract
A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.

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Citations
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Peak power reduction methods in distributed charge pump systems

TL;DR: In this paper, a distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power.
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TL;DR: A charge pump circuit includes a first and second charge pumps, each of which has a boosting unit to respectively initialize and boost a voltage, a transmission transistor to transmit the boosting voltage to an output node, and a control unit to control the transmission transistor.
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Data-driven charge-pump transmitter for differential signaling

TL;DR: In this article, a transmitter combines a direct current (DC) to DC converter including a capacitor with a 2:1 multiplexer to drive a pair of differential signaling lines.
References
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Journal ArticleDOI

On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

TL;DR: An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails.
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An experimental 1.5-V 64-Mb DRAM

TL;DR: In this paper, an accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed to reduce data transmission delay.
Journal ArticleDOI

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

TL;DR: In this article, a cross-coupled voltage doubler with a break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency.
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High voltage generating charge pump circuit

TL;DR: In this paper, a multi-stage charge pump circuit with a particular structure for at least one of the stages is presented, which is especially suited for use in an integrated memory device.
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Charge pump circuit

TL;DR: In this paper, a plurality of driving elements are connected to each other in a cascaded form in order to provide a charge pump circuit preventing influence of body effect, where a substrate connected to the second node, a gate connected to first node, and a drain connected to input terminal, is provided.