Showing papers by "Alberto Sangiovanni-Vincentelli published in 2006"

Complexity of two-level logic minimization

Abstract: The complexity of two-level logic minimization is a topic of interest to both computer-aided design (CAD) specialists and computer science theoreticians. In the logic synthesis community, two-level logic minimization forms the foundation for more complex optimization procedures that have significant real-world impact. At the same time, the computational complexity of two-level logic minimization has posed challenges since the beginning of the field in the 1960s; indeed, some central questions have been resolved only within the last few years, and others remain open. This recent activity has classified some logic optimization problems of high practical relevance, such as finding the minimal sum-of-products (SOP) form and maximal term expansion and reduction. This paper surveys progress in the field with self-contained expositions of fundamental early results, an account of the recent advances, and some new classifications. It includes an introduction to the relevant concepts and terminology from computational complexity, as well a discussion of the major remaining open problems in the complexity of logic minimization

SAT sweeping with local observability don't-cares

Abstract: SAT sweeping is a method for simplifying an shape And/Inverter graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural hashing, simulation, and SAT queries. Due to its robustness and efficiency, SAT sweeping provides a solid algorithm for Booleanreasoning in functional verification and logic synthesis. In previous work, SAT sweeping merges two vertices only if they are functionally equivalent. In this paper we present a significant extension of the SAT-sweeping algorithm that exploits local observability don't-cares (ODCs) to increase the number of vertices merged. We use a novel technique to bound the use of ODCs and thus the computational effort to find them, while still finding a large fraction of them. Our reported results based on a set of industrial benchmark circuits demonstrate that ODC-based SAT sweeping results in significantly more graph simplification with great benefit for Boolean reasoning with a moderate increase in computational effort.

A hierarchical coordination language for interacting real-time tasks

Abstract: We designed and implemented a new programming language called Hierarchical Timing Language (HTL) for hard realtime systems. Critical timing constraints are specified within the language,and ensured by the compiler. Programs in HTL are extensible in two dimensions without changing their timing behavior: new program modules can be added, and individual program tasks can be refined. The mechanism supporting time invariance under parallel composition is that different program modules communicate at specified instances of time. Time invariance under refinement is achieved by conservative scheduling of the top level. HTL is a coordination language, in that individual tasks can be implemented in "foreign" languages. As a case study, we present a distributed HTL implementation of an automotive steer-by-wire controller.

Platform-Based Design of Wireless Sensor Networks for Industrial Applications

Abstract: We present a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN). While the method is quite general, we use extensively an example in the domain of industrial control as it is one of the most promising application of WSN and yet it is largely untouched by it. Our design flow starts from a high level description of the control algorithm and a set of candidate hardware platforms and automatically derives an implementation that satisfies system requirements while optimizing for power consumption. To manage the heterogeneity and complexity inherent in this rather complete design flow, we identify three abstraction layers and introduce the tools to transition between different layers and obtain the final solution. We present a case study of a control application for manufacturing plants that shows how the methodology covers all the aspects of the design process, from conceptual description to implementation.

Ariadne: a Framework for Reachability Analysis of Hybrid Automata

Abstract: In this paper we introduce the problem of reachability analysis of hybrid automata to decide safety properties. Then we describe ARIADNE, an in-progress open environment to design algorithms for computing with hybrid automata. We show that ARIADNE relies on a rigorous computable analysis theory to represent geometric objects, in order to achieve provable approximation bounds along the computations. The proposed tool differs from existing ones because it relies on a sound theoretical basis for the semantics of operators in continuous space and time, making available exact and approximate, but error-bounded operations on geometric points and sets. Currently the geometry module is substantially completed, and work is in progress on the evaluation module. As a first application, we will use ARIADNE to compute the reachable sets of a challenging collection of benchmarks whose safety properties have practical interest.

Classification, Customization, and Characterization: Using MILP for Task Allocation and Scheduling

Abstract: Task allocation and scheduling for heterogeneous multicore platforms must be automated for such platforms to be successful. Techniques such as Mixed Integer Linear Programming (MILP) provide the ability to easily customize the allocation and scheduling problem to application or platform-specific peculiarities. The representation of the core problem in a MILP form has a large impact on the solution time required. In this paper, we investigate a variety of such representations and propose a taxonomy for them. A promising representation is chosen with extensive computational characterization. The MILP formulation is customized for a multimedia case study involving the deployment of a Motion JPEG encoder application onto a Xilinx Virtex II Pro FPGA platform. We demonstrate that our approach can produce solutions that are competitive with manual designs.

Interchange format for hybrid systems : Abstract semantics

Abstract: In [1] we advocated the need for an interchange format for hybrid systems that enables the integration of design tools coming from many different research communities. In deriving such interchange format the main challenge is to define a language that, while presenting a particular formal semantics, remains general enough to accommodate the translation across the various modeling approaches used in the existing tools. In this paper we give a formal definition of the syntax and semantics for the proposed interchange format. In doing so, we clearly separate the structure of a hybrid system from the semantics attached to it. The semantics can be considered an abstract semantics in the sense that it can be refined to yield the model of computation, or concrete semantics, which, in turn, is associated to the existing languages that are used to specify hybrid systems. We show how the interchange format can be used to capture the essential information across different modeling approaches and how such information can be used in the translation process.

Embedding Mixed-Signal Design in Systems-on-Chip Innovative approaches and new design methodologies are needed to integrate digital, analog and RF components in CMOS systems-on-a-chip smaller than 100 nm.

Abstract: With semiconductor technology feature size scal- ing below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining intrinsic device gains. Addres- sing these challenges requires innovative solutions, at the technology, circuit, architecture, and design-methodology level. We present some of these solutions, including a struc- tured platform-based design methodology to enable a mean- ingful exploration of the broad design space and to classify potential solutions in terms of the relevant metrics.

Embedding Mixed-Signal Design in Systems-on-Chip

Abstract: With semiconductor technology feature size scaling below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining intrinsic device gains. Addressing these challenges requires innovative solutions, at the technology, circuit, architecture, and design-methodology level. We present some of these solutions, including a structured platform-based design methodology to enable a meaningful exploration of the broad design space and to classify potential solutions in terms of the relevant metrics.

Interchange format for hybrid systems: abstract semantics

Abstract: In [1] we advocated the need for an interchange format for hybrid systems that enables the integration of design tools coming from many different research communities. In deriving such interchange format the main challenge is to define a language that, while presenting a particular formal semantics, remains general enough to accommodate the translation across the various modeling approaches used in the existing tools. In this paper we give a formal definition of the syntax and semantics for the proposed interchange format. In doing so, we clearly separate the structure of a hybrid system from the semantics attached to it. The semantics can be considered an “abstract semantics” in the sense that it can be refined to yield the model of computation, or “concrete semantics”, which, in turn, is associated to the existing languages that are used to specify hybrid systems. We show how the interchange format can be used to capture the essential information across different modeling approaches and how such information can be used in the translation process.

FPGA Architecture Characterization for System Level Performance Analysis

Abstract: We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used dynamically during simulation to support performance analysis in a System Level Design environment. The topologies capture systems representing common designs using FPGA technologies of interest. Their characterization is done only once; the results are then used during simulation of actual systems being explored by the designer. Our approach allows a rich set of FPGA architectures to be explored accurately at various abstraction levels to seek optimized solutions with minimale effort by the designer. Too offer an industrial example of our results, we describe the characterization process for Xilinx CoreConnect-based platforms and the integration of this data into the Metropolis modeling environment.

Randomized protocol stack for ubiquitous networks in indoor environment

Abstract: We present a novel protocol architecture for ubiq- uitous networks. Our solution is based on a randomized routing, MAC and duty cycling protocols that allow for performance and reliability leveraging node density. We show how the three layers can be jointly optimized for energy efficiency and we present a completely distributed algorithm that allows for the network to reach the optimal working point and adapt to traffic variations with negligible overhead. Finally, we present a set of simulation results that support our mathematical model.

Exploring Trade-off’s Between Centralized versus Decentralized Automotive Architectures Using a Virtual Integration Environment

Abstract: The large variety of architectural dimensions in automotive electronics design, for example, bus protocols, number of nodes, sensors and actuators interconnections and power distribution topologies, makes architecture design task a very complex but crucial design step especially for OEMs. This situation motivates the need for a design environment that accommodates the integration of a variety of models in a manner that enables the exploration of design alternatives in an efficient and seamless fashion. Exploring these design alternatives in a virtual environment and evaluating them with respect to metrics such as cost, latency, flexibility and reliability provide an important competitive advantage to OEMs and help minimize integration risks later in the design cycle. In particular, the choice of the degree of decentralization of the architecture has become a crucial issue in automotive electronics. In this paper, we demonstrate how a rigorous methodology (Platform-Based Design) and the Metropolis framework can be used to find the balance between centralized and decentralized architectures.

Uniprocessor Scheduling Under Precedence Constraints

Abstract: In this paper we present a novel approach to the constrained scheduling problem, while addressing a more general class of constraints that arise from the timing requirements on real-time embedded controllers and from the implementation of mixed data-flow/event-driven real-time systems. We provide general necessary and sufficient conditions for scheduling under precedence constraints and derive sufficient conditions for two well-known scheduling policies. We define mathematical problems that provide optimum priority and deadline assignments, while ensuring both precedence constraints and system’s schedulability.We show how these problems can be relaxed to corresponding ILP formulations leveraging on available solvers.

Schedulability Analysis of Petri Nets Based on Structural Properties

Abstract: A schedule of a Petri Net (PN) represents a set of firing sequences that can be infinitely repeated within a bounded state space, regardless of the outcomes of the nondeterministic choices. Schedulability analysis for a given PN answers the question whether a schedule exists in the reachability space of this net. This paper suggests a novel approach for schedulability analysis based solely on PN structure. It shows that unschedulability can be caused by a structural relation among transitions modelling nondeterministic choices. A method based on linear programming for checking this relation is proposed. This paper also presents a necessary condition for schedulability based on the rank of the incidence matrix of the underlying PN. These results shed a light on the sources of unschedulability often found in PN models of embedded multimedia systems.

Performance analysis of collaborative spatio-temporal processing for wireless sensor networks

Abstract: Spatio-temporal processing (STP) is a control tech- nique to increase the quality of the received signals in wireless networks. Outage events have a strong influence not only on the performance of the physical layer, but also on routing, MAC, and application layers. In this paper, we propose an outage- based performance analysis of collaborative STP for wireless sensor networks (WSNs). After an accurate characterization of the wireless channel, we derive the outage statistics as a function of the STP coefficients, and investigate the effects of STP on the probability, average duration and rate of the outage events. Furthermore, we show that a proper control policy for the STP coefficients can be derived according to the requirements from the application and communication layers. Index Terms: Wireless Sensor Networks (WSNs), Spatio-Temporal processing (STP), Fading, Outage, Level Crossing Analysis.

Hybrid systems in automotive electronics design

Abstract: Automotive electronic design is certainly one of the most attractive and promising application domains for hybrid system techniques. Some successful hybrid system applications to automotive model development and control algorithm design have already been reported in the literature. However, despite the significant advances achieved in the past few years, hybrid methods are in general still not mature enough for their effective introduction in the automotive industry design processes at large. In this paper, we take a broad view of the development process for embedded control systems in the automotive industry with the purpose of identifying challenges and additional opportunities for hybrid systems. We identify critical steps in the design flow and extract a number of open problems where hybrid system technology might play an important role.

Functional Model Exploration for Multimedia Applications via Algebraic Operators

Abstract: An optimized functional design space exploration method for multimedia applications is proposed. The basis of the method is a way of representing the dependency and the concurrency of an application in a compact form exploiting algebraic operators and expressions. The optimized design process consists of mapping one of the possible expressions in the application space onto a concurrent architecture. We use the Metropolis design framework to demonstrate the effectiveness of the procedure using an FPGA architecture as the target implementation platform. The advantage of using this platform is the availability of models that approximate well the performance of the final implementation when performing the mapping from function to architecture thus yielding a robust design methodology.

Cooperative Diversity with Disconnection Constraints and Sleep Discipline for Power Control in Wireless Sensor Networks

Abstract: We derive a power control policy for a group of sensor nodes that are monitoring a real-time application sensitive to disconnections (outages) of the communication. Specifically, we suggest that the sensor nodes perform cooperative diversity while running a sleep discipline. After the description of a detailed model of the wireless links, we propose a power minimization algorithm with a constraint expressed in terms of outage probability. Suboptimal solutions are also discussed. Numerical examples are provided for various number of nodes, wireless scenarios and nodes activities. It is argued that nodes with reduced activity show better performance.

Hierarchical Timing Language

Abstract: We have designed and implemented a new programming language for hard real-time systems. Critical timing constraints are specified within the language, and ensured by the compiler. The main novel feature of the language is that programs are extensible in two dimensions without changing their timing behavior: new program modules can be added, and individual program task can be refined. The mechanism that supports time invariance under parallel composition is that different program modules communicate at specified instances of time. Time invariance under refinement is achieved by conservative scheduling of the top level. The language, which assembles real-time tasks within a hierarchical module structure with timing constraints, is called Hierarchical Timing Language (HTL). It is a coordination language, in that individual tasks can be implemented in other languages. We present a distributed HTL implementation of an automotive steer-by-wire controller as a case study.

Communication by sampling in time-sensitive distributed systems

Abstract: In time-sensitive systems writing to and reading from the communication medium is on a purely time-triggered but asynchronous basis. Writes and reads can occur at any time and the data are stored and sustained until overwritten. We study how to maintain data semantics when the duration of the actions change from specification to implementation.In doing so, we rely on tag systems formerly introduced by the authors. The exibility of tag systems allows handling the problem in a formal, yet tractable way.

A Platform-based Design Flow for Kahn Process Networks

Abstract: Effectively implementing multimedia applications on multiprocessor architectures is a key challenge in system-level design. This work explores automated solutions to this problem by considering two separate directions of research. First, the problem is placed within the context of a generalized mapping strategy and the concept of a common semantic domain is developed which is capable of reasoning about the automation techniques that are to be applied. Second, a specialized design flow and associated algorithms are developed to solve this problem. The idea of a common semantic domain is described and its usefulness in other mapping problems is demonstrated. For this particular problem, a common semantic domain is identified and forms the basis of the algorithms which are developed in the design flow. The design flow is divided into four clearly defined steps, to ensure the tractability of optimization problems while obtaining a good overall solution. The separation of the flow into these steps allows prior work from a variety of sources to be used. Efficient heuristics are developed for each step of the design flow. The effectiveness of the heuristics used in this design flow is demonstrated by applying them to an industrial case study.

Yield prediction for 3D capacitive interconnections

Abstract: Capacitive interconnections are very promising structures for high-speed and low-power signaling in 3D packages. Since the performance of AC links, in terms of Band-Width and Bit-Error-Rate (BER), depends on assembly and synchronization accuracy we performed a statistical analysis of assembly procedures and communication circuits. In this paper we present a yield prediction methodology for 3D capacitive links: starting from the analysis of communication circuits and BER measurements, we analyze stacking variability in order to predict reliability and performance. The proposed parametric yield analysis is demonstrated on a test-case, with constrained inter-electrode coupling and operating frequency.

A Framework for Modeling the Distributed Deployment of Synchronous Designs

Abstract: Synchronous specifications are appealing in the design of large scale hardware and software systems because of their properties that facilitate verification and synthesisWhen the target architecture is a distributed system, implementing a synchronous specification as a synchronous design may be inefficient in terms of both size (memory for software implementations or area for hardware implementations) and performance A more elaborate implementation style where the basic synchronous paradigm is adapted to distributed architectures by introducing elements of asynchrony is, hence, highly desirable Building on the tagged-signal model, we present a modeling for the distributed deployment of synchronous design We offer a comparative exposition of various design approaches (synchronous, asynchronous, GALS, latency-insensitive, and synchronous programming) and we provide some insight on the role of signal absence in modeling synchronization in distributed concurrent systems Finally, we compare two distinct methodologies, desynchronization and latency-insensitive design, and we elaborate on possible options to combine their results

Constraints Assisted Modeling and Validation in Metropolis Framework

Abstract: This paper focuses on quantitative constraints specified with logic of constraints (LOC) and coordination constraints with linear temporal logic (LTL) that are used in the specification, modeling, and validation of heterogeneous embedded system design. Quantity annotation is the principal approach for modeling performance information in Metropolis, our experiment platform. Quantitative constraints are then used to enforce and to refine simulation. They can also be used in synthesis settings especially for deciding system level parameters such as scheduling and hardware-software partitioning. Similarly, we utilize LTL in Metropolis to quickly refine the system behavior especially process coordinations. On the validation aspect, LOC and LTL are also used to specify assertions for simulation and for formal verification. We demonstrate our approach with a multimedia example from the industry.

Is“Network” the Next “Big Idea” in Design?

Abstract: As the complexity of nowadays systems continues to grow, we are moving away from creating individual components from scratch, toward methodologies that emphasize composition of re-usable components via the network paradigm. Complex component interactions can create a range of amazing behaviors, some useful, some unwanted, some even dangerous. To manage them, a “science” for network design is evolving, applicable in some surprising areas. In this paper, we consider a few application domains and discus the design challenges involved from a methodology standpoint. From large-scale hardware/software systems, to dynamically adaptive sensor networks, and network-on-chip architectures, these ideas find wide application.

Communication and Co-Simulation Infrastructure for Heterogeneous System Integration

Abstract: With the increasing complexity and heterogeneity of embedded electronic systems, a unified design methodology at higher levels of abstraction becomes a necessity. Meanwhile, it is also important to incorporate the current design practice emphasizing IP reuse at various abstraction levels. However, the abstraction gap prohibits easy communication and synchronization in IP integration and co-simulation. In this paper, we present a communication infrastructure for an integrated design framework that enables co-design and co-simulation of heterogeneous design components specified at different abstraction levels and in different languages. The core of the approach is to abstract different communication interfaces or protocols to a common high level communication semantics. Designers only need to specify the interfaces of the design components using extended regular expressions; communication adapters can then be automatically generated for the co-simulation or other co-design and co-verification purposes.

Homogeneous semantics preserving deployments of heterogeneous networks of embedded systems

Abstract: Tagged systems provide a denotational semantics for embedded systems. A heterogeneous network of embedded systems can be modeled mathematically by a network of tagged systems. Taking the heterogeneous composition of this network results in a single, homogeneous, tagged system. The question this paper addresses is: when is semantics (behavior) preserved by composition? To answer this question, we use the framework of category theory to reason about heterogeneous system composition and derive results that are as general as possible. In particular, we define the category of tagged systems, demonstrate that a network of tagged systems corresponds to a diagram in this category and prove that taking the composition of a network of tagged systems is equivalent to taking the limit of this diagram-thus composition is endowed with a universal property. Using this universality, we are able to derive verifiable necessary and sufficient conditions on when composition preserves semantics.

Synthesis of Low Power NOC Topologies under Bandwidth Constraints

Abstract: We propose an efficient design flow for the automatic synthesis of Networkon-Chip (NOC) topologies. The specification of the problem is given as a netlist of IP cores and their communication requirements. Each IP is characterized by its area. A communication constraint is denoted by its source and destination IP and a minimum bandwidth requirement. Together with the specification, the users provides a percentage of the chip area that they want to allocate for the communication network. Then, given the clock period of the network (that we assume to be synchronous), and a target technology, the proposed design flow explores the entire topology space and returns an optimal NOC where each router has a position and a routing table assigned. We consider two optimality criteria: power consumption and power delay product. Our design flow, which is based on an approximation algorithm, is efficient and highlights the delicate trade-off balance between cost of communication and cost of switching.