D
David Blaauw
Researcher at University of Michigan
Publications - 792
Citations - 32719
David Blaauw is an academic researcher from University of Michigan. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 87, co-authored 750 publications receiving 29855 citations. Previous affiliations of David Blaauw include Texas A&M University & University of Illinois at Urbana–Champaign.
Papers
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Proceedings ArticleDOI
Razor: a low-power pipeline based on circuit-level timing speculation
Daniel J. Ernst,Nam Sung Kim,Shidhartha Das,Sanjay Pant,Rajeev R. Rao,Toan Pham,Conrad H. Ziesler,David Blaauw,Todd Austin,Krisztian Flautner,Trevor Mudge +10 more
TL;DR: A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
Journal ArticleDOI
Drowsy caches: simple techniques for reducing leakage power
TL;DR: It is argued that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.
Journal ArticleDOI
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
TL;DR: In this paper, the authors define and explore near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors.
Journal ArticleDOI
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance
Shidhartha Das,Carlos Tokunaga,Sanjay Pant,Wei-Hsiang Ma,S. Kalaiselvan,Kevin Lai,David Michael Bull,David Blaauw +7 more
TL;DR: This paper presents a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors and demonstrates SER tolerance on the RazorII processor through radiation experiments.
Proceedings ArticleDOI
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
TL;DR: In this paper, the authors show how the simultaneous use of adaptive body biasing (ABB) and dynamic voltage scaling (DVS) can be used to reduce power in high-performance processors.