Showing papers by "David Esseni published in 2018"

Digital and analog TFET circuits: Design and benchmark

Abstract: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

Influence of Interface Traps on Ferroelectric NC-FETs

Abstract: In this letter, we present an intuitive theoretical framework to investigate the influence of interface traps in NC-FETs, operated either as steep-slope or as $g_{m}$ -boosted devices. Our analysis, validated by numerical simulations, shows that the sub-threshold swing can be either improved or degraded by the presence of defects, and that the threshold voltage can be reduced or increased depending on the design of the NC-FET.

Full-band quantum simulation of electron devices with the pseudopotential method: Theory, implementation, and applications

Abstract: This paper presents the theory, implementation, and application of a quantum transport modeling approach based on the nonequilibrium Green's function formalism and a full-band empirical pseudopotential Hamiltonian. We here propose to employ a hybrid real-space/plane-wave basis that results in a significant reduction of the computational complexity compared to a full plane-wave basis. To this purpose, we provide a theoretical formulation in the hybrid basis of the quantum confinement, the self-energies of the leads, and the coupling between the device and the leads. After discussing the theory and the implementation of the new simulation methodology, we report results for complete, self-consistent simulations of different electron devices, including a silicon Esaki diode, a thin-body silicon field effect transistor (FET), and a germanium tunnel FET. The simulated transistors have technologically relevant geometrical features with a semiconductor film thickness of about 4 nm and a channel length ranging from 10 to 17 nm. We believe that the newly proposed formalism may find applications also in transport models based on ab initio Hamiltonians, as those employed in density functional theory methods.

New Design Perspective for Ferroelectric NC-FETs

Abstract: This letter presents a new angle for the design of negative-capacitance FETs, where the target is not a steep sub-threshold swing, but instead an enhancement of the device transconductance in near- and above-threshold region. The new design is robust against an undesired complete ferroelectric switching and the resulting onset of hysteresis, and it is validated using numerical simulations, calibrated against recent experimental data, and for an ultra-thin body, double-gate FET architecture.

A simulation based study of NC-FETs design: off-state versus on-state perspective

Abstract: This paper presents new analytical and numerical models aiming at a better insight about the physics and design of ferroelectric NC-FETs. We argue that a design focused on the off-state and targeting steep slope with negligible hysteresis is unlikely to be successful. A design targeting an enhanced on-state capacitance is instead more feasible, and can improve both sub-threshold swing and on-current. Also, NC-FETs can reduce the temperature sensitivity compared to baseline FETs, but the sensitivity to dielectrics thickness is critical.

Benchmarking of 3-D MOSFET Architectures: Focus on the Impact of Surface Roughness and Self-Heating

Abstract: Tremendous improvements in the fabrication technology have allowed to scale the physical dimensions of the transistors and also to develop different promising 3-D architectures that may allow continuing Moore’s law. In this paper, we perform a comparative delay analysis of different 3-D device architectures and study the impact of surface roughness and self-heating on the on-current using a comprehensive in-house simulation framework comprising Schrodinger, Poisson, and Boltzmann transport equation solvers and comprising relevant scattering mechanisms and self-heating. Our results highlight that parasitic capacitance can alter the relative ranking of the architectures from delay point of view. We demonstrate that surface roughness can cause architecture and material-dependent current degradation, and hence, it is necessary to account for it in simulation-based benchmarking different architectures.

Revised Analysis of Design Options and Minimum Subthreshold Swing in Piezoelectric FinFETs

Abstract: The theoretical limit of sub-threshold swing ( SS ) in the n-type piezoelectric FinFET (Piezo-FinFET) is thoroughly investigated. Gate voltage modulated strain, conduction band edge shift, and the SS are evaluated utilizing physics-based modeling and numerical simulation, indicating a strong dependence of SS on the fin width, crystalline orientation, and physical properties of the piezo-material used in the gate stack. For [001] Si and [111] Ge Piezo-FinFETs with 5-nm fin width and 3-nm PZT-5H thickness, SS values down to 40 mV/decade are achievable after design optimizations. A figure of merit, ${E}_{\text{cr}} {d}_{z3}/{S}_{\text{pie}, 33}$ , is proposed for the piezo-materials in terms of the critical electric field ( ${E}_\text{cr}$ ), the piezoelectric strain constant ( ${d}_{z3}$ ), and the elastic compliance constant ( ${S}_{\text{pie}, 33}$ ), to guide the Piezo-FinFET designs.

Profiling border-traps by TCAD analysis of multifrequency CV-curves in Al 2 O 3 /InGaAs stacks

Abstract: This paper reports physics based TCAD simulations of multi-frequency C-V curves of In0.53Ga0.47As MOSCAPs including the AC response of the border traps. The calculations reproduce the experimental inversion and accumulation capacitance versus frequency, and provide a means to profile the space and energy density of states of border traps. A sensitivity analysis of the results to border traps' distribution is carried out changing the trap volume and the oxide capacitance.

Transport models based on NEGF and empirical pseudopotentials: a computationally viable method for self-consistent simulation of nanoscale devices

Abstract: We present new theoretical developments and applications concerning Non-Equilibrium Green's Functions (NEGF) based transport modelling with an Empirical Pseudopotential (EP) Hamiltonian. We have extended the methodology to include arbitrary crystal orientations and strain conditions, and have reformulated quantum confinement and spatial discretization to improve the computational efficiency.

Guest Editorial Special Issue on 2-D Materials for Electronic, Optoelectronic, and Sensor Devices

Abstract: Silicon CMOS technology has fueled the phenomenal growth in semiconductor electronics over the past several decades. The miniaturization of a transistor, the basic tenet of technology scaling, is at the core of this revolution. Despite several challenges, the innovations in materials, processes, and device architecture have ensured that Moore’s law is still alive and going strong, with 7-nm silicon FinFET technology in volume production. However, over the past couple of decades, there has been a realization that the silicon CMOS technology may reach the end of scaling unless it is augmented and complemented by other semiconductors. For instance, there has been a substantial effort in the research community to integrate other bulk semiconductors such as germanium and III-Vs, into silicon technology.