T
T. Vandeweyer
Researcher at Katholieke Universiteit Leuven
Publications - 25
Citations - 1415
T. Vandeweyer is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Multiple patterning & Wafer. The author has an hindex of 16, co-authored 25 publications receiving 1342 citations.
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Proceedings ArticleDOI
10×10nm 2 Hf/HfO x crossbar resistive RAM with excellent performance, reliability and low-energy operation
Bogdan Govoreanu,Gouri Sankar Kar,Y. Y. Chen,Vasile Paraschiv,Stefan Kubicek,Andrea Fantini,Iuliana Radu,Ludovic Goux,Sergiu Clima,Robin Degraeve,N. Jossart,O. Richard,T. Vandeweyer,K. Seo,Paul Hendrickx,Geoffrey Pourtois,Hugo Bender,L. Altimime,Dirk Wouters,Jorge A. Kittl,Malgorzata Jurczak +20 more
TL;DR: In this paper, the smallest HfO 2 -based resistive RAM (RRAM) cell was reported, featuring a novel Hf/HfO x resistive element stack, with an area of less than 10×10 nm2, fast ns-range on/off switching times at lowvoltages and with a switching energy per bit of <0.1pJ.
Proceedings ArticleDOI
Highly reliable TaO x ReRAM with centralized filament for 28-nm embedded application
Yukio Hayakawa,Atsushi Himeno,Ryutaro Yasuhara,Werner Boullart,E. Vecchio,T. Vandeweyer,Thomas Witters,D. Crotti,Malgorzata Jurczak,S. Fujii,Satoru Ito,Yoshio Kawashima,Yuichiro Ikeda,Akifumi Kawahara,Ken Kawai,Z. Wei,S. Muraoka,Kazuhiko Shimakawa,Takumi Mikawa,Shinichi Yoneda +19 more
TL;DR: For 28-nm embedded application, a TaOx-based ReRAM with precise filament positioning and high thermal stability is proposed, which succeeded for the first time in forming a filament at the cell center.
Proceedings ArticleDOI
Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability
Jerome Mitard,B. De Jaeger,Frederik Leys,Geert Hellings,Koen Martens,Geert Eneman,David P. Brunco,Roger Loo,Jing-Cheng Lin,Denis Shamiryan,T. Vandeweyer,Gillis Winderickx,E. Vrancken,C.H. Yu,K. De Meyer,Matty Caymax,Luigi Pantisano,Marc Meuris,M.M. Heyns +18 more
TL;DR: In this paper, a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA /mum @Vdd= -1V.
Proceedings ArticleDOI
Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
M.J.H. van Dal,Nadine Collaert,G. Doornbos,Georgios Vellianitis,Gilberto Curatola,Bartek Pawlak,Ray Duffy,C. Jonville,Bart Degroote,E. Altamirano,Eddy Kunnen,Marc Demand,Stephan Beckx,T. Vandeweyer,C. Delvaux,Frederik Leys,Andriy Hikavyy,Rita Rooyackers,Monja Kaiser,R. G. R. Weemaes,Serge Biesemans,Malgorzata Jurczak,K.G. Anil,Liesbeth Witters,Rob Lander +24 more
TL;DR: In this paper, the authors investigated scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193 nm immersion lithography and conventional dry etch.
Proceedings ArticleDOI
A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
K. von Arnim,Emmanuel Augendre,A.C. Pacha,T. Schulz,K.T. San,Florian Bauer,Axel Nackaerts,Rita Rooyackers,T. Vandeweyer,Bart Degroote,Nadine Collaert,Abhisek Dixit,R. Singanamalla,Weize Xiong,Andrew Marshall,C.R. Cleavelin,K. Schrufer,Malgorzata Jurczak +17 more
TL;DR: SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration and NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS.