Viraj Y. Sardesai

TL;DR: In this article, a structure and method for fabricating silicide contacts for semiconductor devices is provided, which involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contact of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions.

TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.

TL;DR: In this paper, a gate structure of a transistor on top of a semiconductor substrate is constructed by forming a first and a second disposable spacers adjacent to the first and second sidewall of the gate structure.

TL;DR: In this article, a method for planarizing a dielectric layer on a semiconductor wafer is provided, where the wafer was first coated with resist and then exposed to an etchant such as RIE to etch the dielectrics material not covered by the resist and forming a profiled layer.

TL;DR: In this paper, a low-temperature process for forming a highly conformal barrier film during integrated circuit manufacture by low pressure chemical vapor deposition (LPCVD) is described, which includes the following steps: First, the process provides ammonia and a silicon-containing gas selected from the group consisting of silane, dichlorosilane, bistertiarybutylaminosilanc, hexachlorodisilane.