An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Using a single layer of electrically controlled metamaterial, researchers have achieved active control of the phase of terahertz waves and demonstrated high-speed broadband modulation.

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A metamaterial solid-state terahertz phase modulator

The attenuation of low-frequency sound has been a challenging task because the intrinsic dissipation of materials is inherently weak in this regime. Here we present a thin-film acoustic metamaterial, comprising an elastic membrane decorated with asymmetric rigid platelets that aims to totally absorb low-frequency airborne sound at selective resonance frequencies ranging from 100-1,000 Hz. Our samples can reach almost unity absorption at frequencies where the relevant sound wavelength in air is three orders of magnitude larger than the membrane thickness. At resonances, the flapping motion of the rigid platelets leads naturally to large elastic curvature energy density at their perimeter regions. As the flapping motions couple only minimally to the radiation modes, the overall energy density in the membrane can be two-to-three orders of magnitude larger than the incident wave energy density at low frequencies, forming in essence an open cavity.

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Dark acoustic metamaterials as super absorbers for low-frequency sound

This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

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FinFET scaling to 10 nm gate length

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124/spl mu/m/sup 2/ half-cell) and full 8T (0.1998/spl mu/m/sup 2/) cells to date.

https://www.bioee.ee.columbia.edu/courses/upload/Bibliography/chang_vlsitech_2005.pdf?origin=publication_detail

Stable SRAM cell design for the 32 nm node and beyond

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.

Extension and source/drain design for high-performance FinFET devices

The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

Fin fet devices from bulk semiconductor and method for forming

The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.

Finfet SRAM cell using low mobility plane for cell stability and method for forming

A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

David M. Fried

Papers

Stable SRAM cell design for the 32 nm node and beyond

Extension and source/drain design for high-performance FinFET devices

Fin fet devices from bulk semiconductor and method for forming

Finfet SRAM cell using low mobility plane for cell stability and method for forming

Strained Fin FETs structure and method