Journal ArticleDOI
Extension and source/drain design for high-performance FinFET devices
J. Kedzierski,Meikei Ieong,E.J. Nowak,Thomas S. Kanarsky,Ying Zhang,Ronnen Andrew Roy,Diane C. Boyd,David M. Fried,Hon-Sum Philip Wong +8 more
TLDR
In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.Abstract:
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the and directions showing different transport properties.read more
Citations
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Journal ArticleDOI
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance
TL;DR: In this article, the authors focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures using new non-classical CMOS structures.
Journal ArticleDOI
Analysis of the parasitic S/D resistance in multiple-gate FETs
TL;DR: In this article, the authors analyzed the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, s/D geometry-based analytical model, which was validated using three-dimensional device simulations and experimental results.
Journal ArticleDOI
Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs
TL;DR: In this paper, the impact of strain on carrier mobility in Si n-and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate is discussed.
Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance
TL;DR: In this paper, the authors proposed several new material and structural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs.
Journal ArticleDOI
Nanoscale FinFETs with gate-source/drain underlap
TL;DR: In this article, the authors show that gate-source/drain (G-S/D) underlap can be achieved via large, doable straggle in the S-D fin-extension doping profile.
References
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Proceedings ArticleDOI
Sub 50-nm FinFET: PMOS
Xuejue Huang,Wen-Chin Lee,C. Kuo,D. Hisamoto,Leland Chang,J. Kedzierski,E. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Nanoscale CMOS
TL;DR: This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime from the point of view of device physics, device technology, and power consumption and speculate on the future ofCMOS for the coming 15-20 years.
Proceedings ArticleDOI
Sub-20 nm CMOS FinFET technologies
Yang-Kyu Choi,Nick Lindert,Peiqi Xuan,S. Tang,Daewon Ha,E. Anderson,T.-J. King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported, which is a more manufacturable process and has less overlap capacitance.
Proceedings ArticleDOI
A folded-channel MOSFET for deep-sub-tenth micron era
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,E. Anderson,Hideki Takeuchi,K. Asano,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a quasi-planar fold-channel transistor structure was proposed for the vertical double-gate SOI MOSFETs, which improved the short channel effect immunities.
Journal ArticleDOI
Nanoscale CMOS spacer FinFET for the terabit era
TL;DR: In this paper, a spacer lithography process was developed to make a sub-40nm Si-fin structure for a double-gate FinFET with conventional dry etching for the first time.