Showing papers by "Eric Beyne published in 2004"

Method for producing electrical through hole interconnects and devices made thereof

Abstract: The invention relates to a method for the fabrication of a device comprising electrical through hole interconnects. In one embodiment, the method comprises anisotropical dry etching of a patternable dielectric material within a substrate hole. One aspect of the invention provides a novel method for producing via or through hole interconnects between microelectronic elements, which is relatively easy to perform and can be applied relatively cheaply compared to the state of the art. The method should, for instance, be applicable in thin chip technology as MCM (Multi Chip Module) and system in a package (SIP) technology.

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

Abstract: In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.

3D interconnection and packaging: impending reality or still a dream?

Abstract: Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).

Mechanical FEM Simulation of bonding process on Cu lowK wafers

Abstract: Major changes are currently happening at the back-end-of-line of integrated circuit processing. New materials are introduced to achieve better electrical performance. The drawback of these new materials is their different mechanical behavior compared to the traditionally used materials. LowK materials, used to replace silicon oxide as dielectric, are very soft and thus provide a low mechanical stiffness. The transition from gold wire to copper wire for the bonding process requires higher forces during the bonding process to form a bond due to the higher hardness of the copper. This leads to higher stresses in the structure. Finally, copper replaces aluminum as interconnection metal. In this study, the induced stresses during the wire bonding process are studied. In the first part, a contact analysis is performed to model the bond formation. The diameter of the bond is recorded as a function of the applied force. The yield stress of the bond material can be estimated by comparing these simulation results to experimental data. In the second part, the stresses in the bond pad are studied. The influence of different lowK materials and interconnection materials is investigated for different configurations of the bond pad. The comparison with the traditionally used materials is made.

SOP integration and codesign of antennas

Abstract: The successful deployment of wireless systems requires the integration of small, cost-effective antennas while preserving a reasonable electrical performance in the required bandwidth. This paper begins with a short overview of the most important antenna characteristics, and then uses these to describe the minimum requirements and fundamental performance-size limits for electrically small integrated antennas. The performance-size tradeoff is further illustrated by the design of a planar integrated antenna for WLAN. Codesign guidelines are given to avoid parasitic coupling between the integrated antenna and RF circuits. A concluding comparison is made between on-chip and on-package integration of a small antenna for microwave and millimeter wave systems.

Hermal cycling reliability of snagcu and snpb solder joints: a comparison for several ic-packages

Abstract: This paper deals with a comparison study between SnPb and SnAgCu solder joint reliability. The comparison is based on non-linear finite element modellin. Three packages have been selected: silicon CSP, underfilled flip chip and QFN package. Also the effect of thermal cycling conditions has been investigated. Comparing the induced inelastic strains in the solder joint, the leadfree SnAgCu generally scores better thanks to the lower creep strain rate. On the other hand for the CSP and flip chip package, SnAgCu scores worse for the more extreme loading conditions when the inelastic dissipated energy density is selected as damage parameter. The main reason is that due to the lower creep strain rate, the stresses become higher for SnAgCu resulting in higher hysteresis loops with more dissipated energy per cycle. For the QFN package, SnAgCu scores much better.

Photopatternable silicone compositions for electronic packaging applications

Abstract: A growing need for low stress high temperature thick film materials has prompted the development of new spin-coatable photopatternable silicones (Dow Corning WL-5000 series) to assist manufactures in building the next generation of electronic devices. These new negative-tone materials can be easily coated onto electronic substrates and patterned using standard i-line and broadband lithographic processes. Films ranging from 6 to 50 μm have been demonstrated with patterned features resolved to an aspect ratio of less than 1.3. The etched regions provide a sloped sidewall and curved surfaces to facilitate metallization processes. The films are cured at low temperatures (150 to 250°C) to provide low modulus values in the range of 150 to 500 MPa, are inherently hydrophobic, and are based on cure chemistry that is acid free and delivers thermally stable cross-links. As a result, the films show very little shrinkage during thermal cure (~2%), do not require extended high temperature processing, and provide a very low residual stress (<8 MPa). They also show excellent thermal stability and mechanical integrity when exposed to high temperatures. A simple wet process has been developed to facilitate film rework and allow for sacrificial layer applications.

Nanohardness study of CoSn/sub 2/ intermetallic layers formed between CO UBM and Sn flip-chip solder joints

Abstract: The possibility to use Co as UBM for Pb-free solder joints is related to the reliability of the formed intermetallic layers at the solder-UBM interface. The interdiffusion reaction results in a layer of CoSn/sub 2/ intermetallic, which was tested by means of nanoindentation. A nanohardness of 2Gpa was measured, which is lower then the one of Ag/sub 3/Sn, Cu/sub 3/Sn or Cu/sub 6/Sn/sub 5/, reported in the literature. This makes the chances of brittle behaviour of this intermetallic very low, which is confirmed by SEM examinations. The measured low hardness of the CoSn/sub 2/ intermetallic layer and the gradual change of the hardness in the stack Co-CoSn/sub 2/-Sn suggest that this interface will be very stable and reliable during the lifetime of the solder joint.

FEM study of deformation and stresses in copper wire bonds on Cu lowK structures during processing

Abstract: Copper low-k structures are industry's choice to meet new requirements in terms of lower trace resistance, lower electrical losses, higher current densities and higher speeds in the back end of line interconnects of ICs. However, the reliability of such structures is a primary concern. In this study, the influence of the material properties of both dielectric layer and metal layer on the stresses in the bond pad structure is discussed. We consider a simplified bond pad structure with a blanket dielectric layer below a single damascene Cu in oxide layer. The pressure from the deforming bond on the bond pad is used as loading. A tolerance analysis points out that the Poisson ratio of the dielectric layer has the largest impact on both von Mises and maximal principal stress in the dielectric layer, while the influence of the stiffness of the dielectric layer on the stresses in the dielectric layer is limited. The stresses in the metal layer are mainly determined by the Young's modulus of both dielectric layer and metal layer. Comparing the value of the maximal principal stress in the metal layer to the ultimate tensile strength reveals that these critical values can be reached during the bonding process, leading to deformation of the bond pad.

Accurate RF electrical characterization of CSPs using MCM-D thin film technology

Abstract: The thin film multilayer multichip module-deposited (MCM-D) technology of IMEC is used for characterising the RF electrical performance of two types of chip scale packages (CSPs). The measurement technique called MCM-on-package-on-MCM (MoPoM) enables accurate measurements and de-embedding in the gigahertz (GHz) range of frequencies. Wafer processing of the MCM-D technology allows for several design structures to be integrated on a single mask. The packages chosen are a 120-pin plastic ball grid array (PBGA) and an 80-pin polymer stud grid array (PSGA). Lumped element models extracted from measurements and three-dimensional simulations show good agreement with the measurements up to 6 GHz for the BGA and the PSGA. The electrical performance of the packages is compared at 1.8 GHz (GSM), 2.4 GHz (Bluetooth), and 5.2 GHz (HiperLAN) and at 5.2 GHz both the packages exhibit a return loss of lower than -10 dB and hence cannot be used in most cases without design improvement. We also show that the influence of encapsulant is significant while transmission line detuning due to the package is not significant at microwave frequencies. We also briefly mention about the crosstalk effects. We demonstrate the significant degradation in the performance of a 5.2 GHz MCM-D low noise amplifier (LNA) after packaging. A significant improvement in package performance is observed by conjugate matching the package interconnects.

Extending on-die wiring hierarchy with wafer level packaging concepts

Abstract: Wafer level package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.

Pulsed DC Sputtered Aluminum Nitride: A Novel Approach To Control Stress And C-axis Orientation

Abstract: This paper reports on a novel low temperature sputter deposition of AlN on an Al substrate, yielding films with stresses and crystalline orientation comparable to those of films deposited on Pt. The study focuses on the importance of the initial film growth step on both the stress and crystalline orientation of the film. The AlN layer is deposited using Pulsed DC (250 kHz, 90% duty cycle) magnetron reactive sputtering (93% N2, 7% Ar) using an Al target. The substrates are 150mm Si wafers with an aluminum seed layer (100 nm). The thickness of the AlN films is ≈2.5µm with uniformity across the wafer of 0.4%. The films were deposited in 4 passes of 0.625µm each to avoid overheating of the substrate. The influence of the substrate bias (0 V, 80 V and 120V) and argon pre-sputtering of the aluminum substrate been investigated. The film stress, and to a smaller extent the crystalline orientation, were mainly driven by the properties of the film deposited during the first pass. The bias is useful at the beginning of the film growth for stress control. This study suggests that it is beneficial not to use bias during the entire film deposition. With this approach, it was possible to deposit c-axis oriented AlN layers on Al with a FWHM of the rocking curve of 1.63° and low stress (<300MPa).

Multimodal characterization of planar microwave structures

Abstract: In this paper, a generalized deembedding technique is presented. It provides a multimodal characterization for microwave devices fed with planar guiding structures of arbitrary configurations. Instead of the conventional scattering matrix, the proposed technique leads to the multimodal scattering matrix. This matrix describes all possible kinds of mutual coupling between the different modes present on the feeding ports. In order to achieve this task, the feeding planar guiding structures are analyzed a priori using a full-wave two-dimensional solver. The generalizability of the proposed deembedding technique is demonstrated by characterizing a couple of coplanar-waveguide-based discontinuities. The results show that the proposed technique provides a rigorous and a detailed characterization.

Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

Abstract: The low fatigue resistance of solder joints limits the reliability of many types of electronic packages. In this study, the reliability of a wafer level package (WLP) was optimized by introducing a flexible silicone bump between the solder joint and the chip in order to buffer the strains and stresses in the solder during thermal cycling. Silicones are non-conductive materials and therefore a metal layer must be applied over the silicone bump for electrical conductivity. The reliability of the package was optimized by balancing the reliability of the solder joint with that of the metallization. The thermomechanical behavior of the eutectic SnPb solder joints and copper metallization was analyzed using a non-linear 3D finite element model (FEM) and accelerated thermal test cycles. Failure analysis after traditional reliability tests of an actual wafer level package shows good agreement with FEM predictions.

Method for producing electrical through hole interconnects

Abstract: The present invention is related to a method for the production of isolated through hole connects in a substrate comprising the steps of: A) providing a substrate (1), B) dry etching the substrate (1), forming at least one substrate hole (2), C) depositing a layer of conducting material (15) on the bottom and on the sidewalls of the substrate hole (2) and possibly on top of the rest of said substrate's surface, thereby transforming the substrate hole (2) into a conductor hole, D) depositing a positive working photo resist (22), E) opening said photo resist (22) at the bottom (23) of said conductor hole, F) bottom-up electroplating a Cu-post (24), G) stripping the photo-resist (22), H) stripping the layer of conducting material (15), I) depositing a layer of planarising dielectric material (25), filling the gap between the conductor hole and said Cu-post, J) depositing and patterning a metal interconnect pattern, K) depositing a second layer (27) of a second dielectric material, L) Mechanical back grinding the substrate, such that it is 10 to 50 micrometer thicker than the actual Cu-post, M) Plasma etching the substrate on the backside, stopping on the Cu-post, N) Solder ball (8) attachment to the Cu-post.

Influence Of Solder Joint Shape On The Thermo-Mechanical Reliability Of CSP's

Abstract: Not only the stand-off height but also the shape of a solder joint has a strong influence on the joint reliability under temperature cycling. The shape determines the size of the local stress and strain concentrations. It is therefore very important to know well the joint shape after reflow. In a previous paper closed analytical expressions were derived for liquid bump shapes, as a function of pad size and bump height [1]. The bump deformation as a function of the chip weight could be derived from the force constant. In the present paper closed analytical expressions are derived for the force constant for liquid bumps having unequal spherical pad sizes. It turns out that the force constant for compression can be optimized as a function of the ratio of those pad sizes. The shape of the bump and especially the contact angle is of interest for modeling activities where geometrical effects do play a role. Furthermore from the variation in bumps heights on a chip an estimate can be made of the tilt of the chip...

Method for producing electrical through hole interconnects and corresponding devices

Abstract: The invention is related to a method for the fabrication of a device comprising electrical through hole interconnects, comprising the steps of: A) bonding a silicon die (13) to a substrate comprising an open contact (11), whereby said silicon die (13) has an internal contact or an internal contact is created, said internal contact being isolated by a first layer of a first dielectric material, B) dry etching said silicon die (13), forming at least one substrate hole (14), until said first layer of said first dielectric material in said internal contact is reached, C) dry etching said first layer of said first dielectric material at the bottom of said substrate hole (14), D) depositing a second layer (16) of a second dielectric material, said substrate hole (14) thereby being filled, E) dry etching in said second layer of said second dielectric material within said substrate hole in said silicon die, forming a dielectric hole (18) within said substrate hole, F) depositing a thick metal layer (19), creating an interconnect between said open contact (11) and said internal contact (12), thereby transforming said dielectric hole into a conductor hole, and etching said thick metal layer (19), G) depositing a third layer (20) of a third dielectric material, thereby filling said conductor hole.