The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

State of the Art and Future Perspectives in Advanced CMOS Technology.

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure.

Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors

The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

The Challenges of Advanced CMOS Process from 2D to 3D

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions ( $L_{G}= 40$ nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub-20 nA/ $\mu \text{m}~I_{\mathrm{\scriptscriptstyle off}}$ at $V_{\mathrm {{\text {DD}}}}= -0.5$ V and $L_{G}= 40$ nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any $L_{G}= 40$ -nm Ge pMOS channel device.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.

GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node

We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.

https://hal-cea.archives-ouvertes.fr/cea-01973383/document

J. Daranlot

Papers

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain