C
C. Vizioz
Researcher at University of Grenoble
Publications - 44
Citations - 1430
C. Vizioz is an academic researcher from University of Grenoble. The author has contributed to research in topics: Nanowire & Metal gate. The author has an hindex of 18, co-authored 44 publications receiving 1248 citations.
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Proceedings ArticleDOI
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration
Arnaud Hubert,Etienne Nowak,K. Tachi,V. Maffini-Alvaro,C. Vizioz,Christian Arvet,J. P. Colonna,J.M. Hartmann,Virginie Loup,L. Baud,S. Pauliac,Vincent Delaye,C. Carabasse,G. Molas,Gerard Ghibaudo,B. De Salvo,O. Faynot,Thomas Ernst +17 more
TL;DR: In this article, the Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter) is extended to an independent double gate memory architecture, called φ-Flash.
Proceedings ArticleDOI
15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET
Cecilia Dupre,Arnaud Hubert,S. Becu,M. Jublot,V. Maffini-Alvaro,C. Vizioz,F. Aussenac,Christian Arvet,Sébastien Barnola,J.M. Hartmann,G. Garnier,F. Allain,J. P. Colonna,Maurice Rivoire,L. Baud,S. Pauliac,Virginie Loup,Thierry Chevolleau,P. Rivallin,Bernard Guillaumot,Gerard Ghibaudo,O. Faynot,Thomas Ernst,Simon Deleonibus +23 more
TL;DR: In this paper, a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET is reported.
Proceedings ArticleDOI
Performance and design considerations for gate-all-around stacked-NanoWires FETs
Sylvain Barraud,V. Lapras,Bernard Previtali,M.-P. Samson,Joris Lacord,Sebastien Martinie,Marie-Anne Jaud,Sotirios Athanasiou,François Triozon,Olivier Rozeau,J.M. Hartmann,C. Vizioz,C. Comboroure,Francois Andrieu,Jean-Charles Barbe,Maud Vinet,Thomas Ernst +16 more
TL;DR: In this paper, Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs are compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options.
Proceedings ArticleDOI
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
Sylvain Barraud,V. Lapras,M.-P. Samson,L. Gaben,Laurent Grenouillet,V. Maffini-Alvaro,Yves Morand,J. Daranlot,N. Rambal,B. Previtalli,Shay Reboh,Claude Tabone,R. Coquand,E. Augendre,Olivier Rozeau,J.M. Hartmann,C. Vizioz,Christian Arvet,Patricia Pimenta-Barros,Nicolas Posseme,Virginie Loup,C. Comboroure,C. Euvrard,V. Balan,I. Tinti,G. Audoit,Nicolas Bernier,David Cooper,Zineb Saghi,F. Allain,A. Toffoli,O. Faynot,Maud Vinet +32 more
TL;DR: In this article, vertically stacked horizontal Si nano-wire (NW) /-MOSFETs fabricated with a replacement metal gate (RMG) process are integrated with inner spacers and SiGe source-drain (S/D) stressors.
Proceedings ArticleDOI
50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process
S. Monfray,Thomas Skotnicki,Yves Morand,S. Descombes,Philippe Coronel,Pascale Mazoyer,S. Harrison,P. Ribot,Alexandre Talbot,Didier Dutartre,Michel Haond,R. Palla,Y. Le Friec,Francois Leverd,M. E. Nier,C. Vizioz,D. Louis +16 more
TL;DR: In this paper, both GAA and bulk devices were shown to be operational on the same chip, and the first-time results were very encouraging: I/sub on/=170 /spl mu/A/spl mu /m@ 1.2 V and gate oxide of 20 /spl Aring.