C
C. Comboroure
Researcher at STMicroelectronics
Publications - 12
Citations - 501
C. Comboroure is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Nanowire & Metal gate. The author has an hindex of 9, co-authored 12 publications receiving 399 citations.
Papers
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Journal ArticleDOI
Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm
Sylvain Barraud,R. Coquand,Mikael Casse,M. Koyama,Jean-Michel Hartmann,V. Maffini-Alvaro,C. Comboroure,C. Vizioz,F. Aussenac,Olivier Faynot,Thierry Poiroux +10 more
TL;DR: In this paper, the electrostatic and performance of cylindrical silicon nanowire (NW) MOSFETs with an omega-shaped gate and diameters down to 8 nm are investigated.
Proceedings ArticleDOI
Performance and design considerations for gate-all-around stacked-NanoWires FETs
Sylvain Barraud,V. Lapras,Bernard Previtali,M.-P. Samson,Joris Lacord,Sebastien Martinie,Marie-Anne Jaud,Sotirios Athanasiou,François Triozon,Olivier Rozeau,J.M. Hartmann,C. Vizioz,C. Comboroure,Francois Andrieu,Jean-Charles Barbe,Maud Vinet,Thomas Ernst +16 more
TL;DR: In this paper, Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs are compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options.
Proceedings ArticleDOI
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
Sylvain Barraud,V. Lapras,M.-P. Samson,L. Gaben,Laurent Grenouillet,V. Maffini-Alvaro,Yves Morand,J. Daranlot,N. Rambal,B. Previtalli,Shay Reboh,Claude Tabone,R. Coquand,E. Augendre,Olivier Rozeau,J.M. Hartmann,C. Vizioz,Christian Arvet,Patricia Pimenta-Barros,Nicolas Posseme,Virginie Loup,C. Comboroure,C. Euvrard,V. Balan,I. Tinti,G. Audoit,Nicolas Bernier,David Cooper,Zineb Saghi,F. Allain,A. Toffoli,O. Faynot,Maud Vinet +32 more
TL;DR: In this article, vertically stacked horizontal Si nano-wire (NW) /-MOSFETs fabricated with a replacement metal gate (RMG) process are integrated with inner spacers and SiGe source-drain (S/D) stressors.
Proceedings ArticleDOI
First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
Laurent Brunet,Perrine Batude,Claire Fenouillet-Beranger,P. Besombes,L. Hortemel,F. Ponthenier,Bernard Previtali,Claude Tabone,A. Royer,C. Agraffeil,C. Euvrard-Colnat,A. Seignard,Christophe Morales,F. Fournel,L. Benaissa,Thomas Signamarcheix,Pascal Besson,M. Jourdan,R. Kachtouli,V. Benevent,J.M. Hartmann,C. Comboroure,N. Allouti,Nicolas Posseme,C. Vizioz,Christian Arvet,Sébastien Barnola,Sebastien Kerdiles,L. Baud,L. Pasini,C.-M. V. Lu,F. Deprat,Alain Toffoli,G. Romano,C. Guedj,Vincent Delaye,Frederic Boeuf,O. Faynot,Maud Vinet +38 more
TL;DR: In this article, a full 3D CMOS over CMOS CoolCube integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.
Proceedings ArticleDOI
Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width
R. Coquand,S. Barraud,M. Casse,P. Leroux,C. Vizioz,C. Comboroure,Pierre Perreau,E. Ernst,M.-P. Samson,V. Maffini-Alvaro,Claude Tabone,Sébastien Barnola,Daniela Munteanu,Gerard Ghibaudo,Stephane Monfray,Frederic Boeuf,Thierry Poiroux +16 more
TL;DR: In this paper, a Tri-Gate Nanowire (TGNW) FET with high-k/metal gate is studied as an alternative way to planar devices for the future CMOS technological nodes (14nm and beyond).