L
L. Gaben
Researcher at University of Grenoble
Publications - 3
Citations - 118
L. Gaben is an academic researcher from University of Grenoble. The author has contributed to research in topics: Nanowire & Field-effect transistor. The author has an hindex of 3, co-authored 3 publications receiving 87 citations.
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Proceedings ArticleDOI
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
Sylvain Barraud,V. Lapras,M.-P. Samson,L. Gaben,Laurent Grenouillet,V. Maffini-Alvaro,Yves Morand,J. Daranlot,N. Rambal,B. Previtalli,Shay Reboh,Claude Tabone,R. Coquand,E. Augendre,Olivier Rozeau,J.M. Hartmann,C. Vizioz,Christian Arvet,Patricia Pimenta-Barros,Nicolas Posseme,Virginie Loup,C. Comboroure,C. Euvrard,V. Balan,I. Tinti,G. Audoit,Nicolas Bernier,David Cooper,Zineb Saghi,F. Allain,A. Toffoli,O. Faynot,Maud Vinet +32 more
TL;DR: In this article, vertically stacked horizontal Si nano-wire (NW) /-MOSFETs fabricated with a replacement metal gate (RMG) process are integrated with inner spacers and SiGe source-drain (S/D) stressors.
Proceedings ArticleDOI
Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length
P. Nguyen,S. Barraud,Claude Tabone,L. Gaben,M. Casse,F. Glowacki,J.M. Hartmann,M.-P. Samson,V. Maffini-Alvaro,C. Vizioz,Nicolas Bernier,C. Guedj,C. Mounet,O. Rozeau,A. Toffoli,F. Alain,Daniel Delprat,Bich-Yen Nguyen,Carlos Mazure,O. Faynot,M. Vinet +20 more
TL;DR: An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si, evidenced for ultra-scaled p-FET NWs with +90% ION current improvement.
Proceedings ArticleDOI
Opportunities and challenges of nanowire-based CMOS technologies
S. Barraud,M. Casse,L. Gaben,Phuong Nguyen,J.M. Hartmann,M.-P. Samson,V. Maffini-Alvaro,Claude Tabone,C. Vizioz,Christian Arvet,P. Pimenta-Barros,F. Glowacki,N. Bernier,O. Rozeau,Marie-Anne Jaud,Sebastien Martinie,J. Laccord,F. Allain,B. De Salvo,M. Vinet +19 more
TL;DR: In this article, the major assets of NW field effect transistors in leading-edge technology nodes are explained in details, and a particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high density stacked-NWs architectures.