K
Kisik Choi
Researcher at IBM
Publications - 101
Citations - 2165
Kisik Choi is an academic researcher from IBM. The author has contributed to research in topics: Metal gate & Gate dielectric. The author has an hindex of 28, co-authored 100 publications receiving 2091 citations. Previous affiliations of Kisik Choi include SEMATECH & GlobalFoundries.
Papers
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Proceedings ArticleDOI
Fundamental aspects of HfO 2 -based high-k metal gate stack reliability and implications on t inv -scaling
Eduard A. Cartier,Andreas Kerber,Takashi Ando,Martin M. Frank,Kisik Choi,Siddarth A. Krishnan,Barry Linder,Kai Zhao,Frederic Monsieur,James H. Stathis,Vijay Narayanan +10 more
TL;DR: In this paper, a case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric.
Patent
Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures
Takashi Ando,Eduard A. Cartier,Kisik Choi,Wing L. Lai,Vijay Narayanan,Ravikumar Ramachandran +5 more
TL;DR: In this article, the metal containing layer and the diffusion barrier layer are removed and a second anneal is performed to adjust diffusion of the elements in the dielectric layer.
Proceedings ArticleDOI
A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
Kang-ill Seo,Balasubramanian S. Pranatharthi Haran,Dinesh Gupta,Dechao Guo,Theodorus E. Standaert,Ruilong Xie,H. Shang,E. Alptekin,D.I. Bae,Geum-Jong Bae,Carol Boye,H. Cai,D. Chanemougame,Robin Chao,Kangguo Cheng,Jin Cho,Kisik Choi,B. Hamieh,J. G. Hong,Terence B. Hook,L. Jang,Ju-Hwan Jung,R. Jung,Deok-Hyung Lee,B. Lherron,R. Kambhampati,Bomsoo Kim,Hoon Kim,K. Kim,Tae-Chan Kim,S.-B. Ko,Fee Li Lie,Derrick Liu,H. Mallela,Erin Mclellan,Sanjay Mehta,P. Montanini,M. Mottura,J. Nam,S. Nam,F. Nelson,Injo Ok,Chanro Park,Young-Kwan Park,Abhijeet Paul,Christopher Prindle,Ravikumar Ramachandran,Muthumanickam Sankarapandian,V. Sardesai,Andreas Scholze,Soon-Cheon Seo,Jeffrey C. Shearer,Richard G. Southwick,Raghavasimhan Sreenivasan,S. Stieg,Jay W. Strane,Xiao Sun,Min Gyu Sung,Charan V. V. S. Surisetty,Gen Tsutsui,Neeraj Tripathi,Reinaldo A. Vega,Christopher J. Waskiewicz,M. Weybright,C.-C. Yeh,Huiming Bu,Sean D. Burns,Donald F. Canaperi,M. Celik,Matthew E. Colburn,Hemanth Jagannathan,S. Kanakasabaphthy,Walter Kleemeier,Lars W. Liebmann,D. McHerron,Philip J. Oldiges,Vamsi Paruchuri,Terry A. Spooner,James H. Stathis,R. Divakaruni,T. Gow,John Iacoponi,J. Jenq,R. Sampson,Mukesh Khare +84 more
TL;DR: A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate.
Proceedings ArticleDOI
Understanding mobility mechanisms in extremely scaled HfO 2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t -tuning dipoles with gate-first process
Takashi Ando,Martin M. Frank,Kisik Choi,Chang Hwan Choi,John Bruley,Marinus Hopstaken,Matthew Copel,Eduard A. Cartier,Andreas Kerber,Alessandro C. Callegari,Dianne L. Lacey,Stephen L. Brown,Qingyun Yang,Vijay Narayanan +13 more
TL;DR: A novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based MOSFET high-к gate dielectric is demonstrated.
Journal ArticleDOI
HfO2 gate dielectric with 0.5 nm equivalent oxide thickness
H.R. Harris,Kisik Choi,N. Mehta,A. Chandolu,Nivedita Biswas,G. Kipshidze,Sergey A. Nikishin,S. Gangopadhyay,Henryk Temkin +8 more
TL;DR: In this article, the capacitance and voltage curves of as-deposited metal(Ti) insulator-semiconductor structures exhibited large hysteresis and frequency dispersion.