J
Jack T. Kavalieros
Researcher at Intel
Publications - 353
Citations - 10336
Jack T. Kavalieros is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 55, co-authored 351 publications receiving 10238 citations. Previous affiliations of Jack T. Kavalieros include Metz.
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Patent
Semiconductor device with reduced fringe capacitance
TL;DR: In this paper, a non-planar transistor includes a gate electrode and multiple fins, and a trench contact is coupled to the fins, which is formed above the substrate and does not directly contact the substrate.
Patent
Fabrication of nanowire transistors using hard mask layer
TL;DR: The use of at least one hard mask may result in a substantially damage-free uppermost channel nanowire in the multi-stacked nanowires, which may improve the uniformity of the channels and the reliability of the overall multiscale transistors.
Patent
Memory device with multiple memory arrays to facilitate in-memory computation
Jack T. Kavalieros,Ram Krishnamurthy,Sasikanth Manipatruni,Gregory K. Chen,Le Van H,Amrita Mathuriya,Sharma Abhishek A,Raghavan Kumar,Knag Phil,Sumbul Huseyin Ekin,Young Ian A +10 more
TL;DR: In this article, a memory device comprises a first memory array and circuitry, coupled to the second memory array, to perform a data computation based on data stored at the first array.
Patent
Two transistor memory cell using high mobility metal oxide semiconductors
Le Van H,Gilbert Dewey,Marko Radosavljevic,Rafael Rios,Jack T. Kavalieros,Shivaraman Shriram,Mesut Meterelliyoz +6 more
TL;DR: In this paper, a two transistor memory cell is described that uses high mobility amorphous oxide semiconductors, where the source of the charging transistor is coupled to the gate of the sensing transistor, and a gate electrode in a third metal layer is coupled with the source.
Patent
Stacked thin-film transistor based embedded dynamic random-access memory
Abhishek Sharma,Alzate-Vinasco Juan G,Fatih Hamzaoglu,Sell Bernhard,Wang Pei-Hua,Le Van H,Jack T. Kavalieros,Tahir Ghani,Umut Arslan,Lajoie Travis W,Ku Chieh-Jen +10 more
TL;DR: Stacked TFT based eDRAM as discussed by the authors allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.