An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

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Nanoscale thermal transport. II. 2003–2012

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, Sn02, or In203. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, Sn02or In2O3, the substantially insulating ZnO, Sn02, or In203 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Transistor structures and methods for making the same

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

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MoS2 transistors with 1-nanometer gate lengths

Epitaxial film on a nanoscale structure

Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 1 0) plane on a (110) plane of the silicon.

High electron mobility transistor (HEMT) and method of fabrication

FIELD: chemistrySUBSTANCE: method of manufacturing a device based on the material of groups III-V includes the steps of forming a groove in an insulating layer on a silicon substrate, the first buffer layer based on groups III-V material on a silicon substrate is applied to the groove, the second buffer layer is applied to the first buffer layer based on the material of groups III-V, the channel layer of the device based on the material of group III-V is applied to the second buffer layer based on material of groups III-VEFFECT: invention provides the integration of devices based on the materials of groups III-V of n-type and p-type on a silicon substrate18 cl, 16 dwg

Devices based on selectively grown epitaxial materials of groups iii-v

The invention discloses a non-planar gate all-around device and a manufacturing method thereof. In one embodiment, the device comprises a substrate, and the substrate is provided with a top surface with a first lattice constant. An embedded epitaxial source electrode area and an embedded epitaxial drain electrode area are formed on the top surface of the substrate. The embedded epitaxial source electrode area and the embedded epitaxial drain electrode area have a second lattice constant different from the first lattice constant. Channel nanowires with a third lattice constant are formed between the embedded epitaxial source electrode area and the embedded epitaxial drain electrode area, and are coupled with the embedded epitaxial source electrode area and the embedded epitaxial drain electrode area. In another embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires comprise a bottommost channel nanowire, and a bottom gate isolator is formed on the top surface of the substrate below the bottommost channel nanowire. Gate dielectric layers are formed on and around each channel nanowire. Gate electrodes are formed on the gate dielectric layers, and enclose each channel nanowire.

Non-planar gate all-around device and manufacturing method thereof

Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (eg, B, P, or As) into the adjacent Ge-rich channel region In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region Numerous embodiments, configurations, and variations will be apparent

Jack T. Kavalieros

Papers

Epitaxial film on a nanoscale structure

High electron mobility transistor (HEMT) and method of fabrication

Devices based on selectively grown epitaxial materials of groups iii-v

Non-planar gate all-around device and manufacturing method thereof

Germanium-rich channel transistors including one or more dopant diffusion barrier elements