An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

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Nanoscale thermal transport. II. 2003–2012

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, Sn02, or In203. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, Sn02or In2O3, the substantially insulating ZnO, Sn02, or In203 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Transistor structures and methods for making the same

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

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MoS2 transistors with 1-nanometer gate lengths

An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper III-V material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

Uniform layers formed with aspect ratio trench based processes

A complementary metal oxide semiconductor integrated circuit may be formed with NMOS and PMOS transistors that have high dielectric constant gate dielectric material over a semiconductor substrate. A metal barrier layer may be formed over the gate dielectric. A workfunction setting metal layer is formed over the metal barrier layer and a cap metal layer is formed over the workfunction setting metal layer.

A metal gate electrode semiconductor device

Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.

Group iii-v material transistors employing nitride-based dopant diffusion barrier layer

Die Verfahren der Bildung von Hetero-Schichten mit reduzierter Oberflachenrauhigkeit und Defektdichte auf ortsfremden Oberflachen und die dadurch gebildeten Bauelemente werden beschrieben. In einer Ausfuhrungsform beinhaltet das Verfahren die Bereitstellung eines Substrats mit einer Deckflache mit einer Gitterkonstante und das Auftragen einer ersten Schicht auf der Deckflache des Substrats. Die erste Schicht hat eine Deckflache mit einer Gitterkonstante, die sich von der Gitterkonstante der Deckflache des Substrats unterscheidet. Die erste Schicht wird gegluht und poliert, um eine polierte Oberflache zu bilden. Eine zweite Schicht wird dann uber der polierten Oberflache aufgetragen.

Methoden der Bildung von Hetero-Schichten mit reduzierter Oberflachenrauhigkeit und Defektdichte auf ortsfremden Oberflächen und die dadurch entstehenden Strukturen

An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

Jack T. Kavalieros

Papers

Uniform layers formed with aspect ratio trench based processes

A metal gate electrode semiconductor device

Group iii-v material transistors employing nitride-based dopant diffusion barrier layer

Methoden der Bildung von Hetero-Schichten mit reduzierter Oberflachenrauhigkeit und Defektdichte auf ortsfremden Oberflächen und die dadurch entstehenden Strukturen

Thin channel region on wide subfin