J
Jack T. Kavalieros
Researcher at Intel
Publications - 353
Citations - 10336
Jack T. Kavalieros is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 55, co-authored 351 publications receiving 10238 citations. Previous affiliations of Jack T. Kavalieros include Metz.
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Patent
Multigate device with recessed strain regions
TL;DR: In this article, the authors proposed a device with a multiple gate body metal gate, which can be used to improve the performance of the device by placing stress material within the recesses of a device.
Patent
Semiconductor device structures and methods of forming semiconductor structures
Justin Brask,Jack T. Kavalieros,Brian S. Doyle,Uday Shah,Suman Datta,Amlan Majumdar,Robert S. Chau +6 more
TL;DR: In this article, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal planes is denser than the second crystal planes and wherein the hard mask was formed on the second plane.
Patent
Process for ultra-thin body soi devices that incorporate epi silicon tips and article made thereby
TL;DR: In this paper, an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor is described.
Patent
High mobility strained channels for fin-based transistors
Stephen M. Cea,Anand S. Murthy,Glenn A. Glass,Daniel B. Aubertine,Tahir Ghani,Jack T. Kavalieros,Roza Kotlyar +6 more
TL;DR: In this article, the authors present techniques for incorporating high mobility strained channels into fin-based transistors (e.g., double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin.
Patent
Transistors with high concentration of boron doped germanium
Anand S. Murthy,Glenn A. Glass,Tahir Ghani,Ravi Pillarisetty,Niloy Mukherjee,Jack T. Kavalieros,Roza Kotlyar,Rachmady Willy,Mark Y. Liu +8 more
TL;DR: In this article, techniques for forming transistor devices having source and drain regions with high concentrations of boron doped germanium are disclosed. But the techniques can be embodied, for instance, in planar or nonplanar transistor devices.