An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

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Nanoscale thermal transport. II. 2003–2012

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, Sn02, or In203. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, Sn02or In2O3, the substantially insulating ZnO, Sn02, or In203 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Transistor structures and methods for making the same

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

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MoS2 transistors with 1-nanometer gate lengths

Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

Apparatus having stacking transistors, method for fabricating stacking transistors and computing device

Techniques are disclosed for a non-planar semiconductor device, a silicon substrate, a silicon germanium barrier layer formed over the silicon substrate, a germanium quantum well layer formed over the silicon germanium barrier layer. In particular, a portion of the germanium quantum well layer comprises a germanium fin structure having a top surface and laterally opposite sidewall surfaces, a top barrier is formed on at least a portion of the germanium fin structure, wherein the top barrier covers the top surface and sidewall surfaces of the germanium fin structure, a gate electrode layer is formed across the fin structure, and a gate dielectric layer is formed between the top barrier and the gate electrode layer.

Non-planar germanium quantum well devices and methods of manufacturing the same

A DRAM integrated circuit device is described in which at least some of the peripheral circuits associated with the memory arrays are provided on a first substrate. The memory arrays are provided on a second substrate stacked on the first substrate, thus forming a DRAM integrated circuit device on a stacked-substrate assembly. Vias that electrically connect the memory arrays on the second substrate to the peripheral circuits on the first substrate are fabricated using high aspect ratio via fabrication techniques.

Stacked-substrate dram semiconductor devices

Halbleitervorrichtung, umfassend: ein Si-Substrat; eine Pufferschicht auf dem Si-Substrat, wobei die Pufferschicht eine GaAs-Keimbildungsschicht, eine erste GaAs-Pufferschicht und eine zweite GaAs-Pufferschicht umfasst; eine Grundsperre auf der Pufferschicht, wobei die Grundsperre einen Bandabstand von mehr als etwa 1,1 eV hat; eine aktive Ge-Kanalschicht auf der Grundsperre, wobei eine Valenzbandversetzung zwischen der Grundsperre und der aktiven Ge-Kanalschicht groser als etwa 0,3 eV ist; und eine obere AlAs-Sperre auf der aktiven Ge-Kanalschicht, wobei die obere AlAs-Sperre einen Bandabstand von mehr als etwa 1,1 eV hat.

P-Kanal-Ge-Transistorstruktur mit hoher Löchermobilität auf Si-Substrat

Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of- line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

Jack T. Kavalieros

Papers

Apparatus having stacking transistors, method for fabricating stacking transistors and computing device

Non-planar germanium quantum well devices and methods of manufacturing the same

Stacked-substrate dram semiconductor devices

P-Kanal-Ge-Transistorstruktur mit hoher Löchermobilität auf Si-Substrat

Integrated circuit die having back-end-of-line transistors