J
Jack T. Kavalieros
Researcher at Intel
Publications - 353
Citations - 10336
Jack T. Kavalieros is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 55, co-authored 351 publications receiving 10238 citations. Previous affiliations of Jack T. Kavalieros include Metz.
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Patent
Modulation-doped multi-gate devices
TL;DR: In this article, modulation-doped multi-gate devices are described, where a substrate has a surface, buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to buffer films, a fin coupled to first barrier films, and a channel region of a multigated device where the channel region is disposed between the source region and the drain region.
Patent
Strain inducing semiconductor regions
TL;DR: In this article, a method to form a strain-inducing semiconductor region is described, where the lattice constant of the semiconductor regions is different from that of the crystalline substrate, and all species of charge-neutral lattice-forming atoms are contained in the crystal substrate.
Patent
Methods for integrating replacement metal gate structures
Jack T. Kavalieros,Justin Brask,Mark L. Doczy,Scott A. Hareland,Matthew V. Metz,Chris Barns,Robert S. Chau +6 more
TL;DR: In this paper, a substrate consisting of a first transistor structure comprising an n-type gate material and a second transistor structure comprised of a p-type metal gate material is provided.
Patent
Field effect transistor with metal source/drain regions
Marko Radosavljevic,Suman Datta,Brian S. Doyle,Jack T. Kavalieros,Justin K. Brask,Mark L. Doczy,Amian Majumdar,Robert S. Chau +7 more
TL;DR: In this article, a gate electrode formed on a gate dielectric layer is formed adjacent the channel region on opposite sides of the gate electrode, and the source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent and in touch with the metal portion.
Journal ArticleDOI
Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit
TL;DR: In this paper, the authors present a capacitance model and extraction based on the application of a lossy transmission line model to the MOS transistor, which properly accounts for the leakage current distribution along the channel and produces a gate length dependent correction factor for the measured capacitance.