J
Jack T. Kavalieros
Researcher at Intel
Publications - 353
Citations - 10336
Jack T. Kavalieros is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Layer (electronics). The author has an hindex of 55, co-authored 351 publications receiving 10238 citations. Previous affiliations of Jack T. Kavalieros include Metz.
Papers
More filters
Patent
Dislocation removal from a group iii-v film grown on a semiconductor substrate
TL;DR: In this article, the authors described dislocations from a group III-V film grown on a semiconductor substrate, where a lattice mismatch exists between the substrate and the first semiconductor film.
Patent
Aspect ratio trapping (art) for fabricating vertical semiconductor devices
Le Van H,Benjamin Chu-Kung,Gilbert Dewey,Jack T. Kavalieros,Ravi Pillarisetty,Willy Rachmady,Marko Radosavljevic,Metz Matthew,Niloy Mukherjee,Robert S. Chau +9 more
TL;DR: In this article, aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductors fabricated there from are described, where a semiconductor device includes a substrate with an uppermost surface having a first lattice constant.
Patent
Making a defect free fin based device in lateral epitaxy overgrowth region
Niti Goel,Benjamin Chu-Kung,Sansaptak Dasgupta,Niloy Mukherjee,Metz Matthew,Le Van H,Jack T. Kavalieros,Robert S. Chau,Ravi Pillarisetty +8 more
TL;DR: In this paper, an electronic device fin is formed by epitaxially growing a first layer of material on a substrate surface at the bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions.
Patent
Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
TL;DR: In this article, a contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening, forming an insulator on the source region, forming a contact metal on the insulator, and filling substantially all of the first opening.
Patent
Hetero-bimos injection process for non-volatile flash memory
TL;DR: In this paper, a hetero-BiMOS injection system consisting of a MOSFET transistor formed on a substrate and a Hetero-bipolar transistor formed within the substrate is described.