An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

A diverse spectrum of technology drivers such as improved thermal barriers, higher efficiency thermoelectric energy conversion, phase-change memory, heat-assisted magnetic recording, thermal management of nanoscale electronics, and nanoparticles for thermal medical therapies are motivating studies of the applied physics of thermal transport at the nanoscale. This review emphasizes developments in experiment, theory, and computation in the past ten years and summarizes the present status of the field. Interfaces become increasingly important on small length scales. Research during the past decade has extended studies of interfaces between simple metals and inorganic crystals to interfaces with molecular materials and liquids with systematic control of interface chemistry and physics. At separations on the order of ∼1 nm, the science of radiative transport through nanoscale gaps overlaps with thermal conduction by the coupling of electronic and vibrational excitations across weakly bonded or rough interface...

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Nanoscale thermal transport. II. 2003–2012

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, Sn02, or In203. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, Sn02or In2O3, the substantially insulating ZnO, Sn02, or In203 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Transistor structures and methods for making the same

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

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MoS2 transistors with 1-nanometer gate lengths

An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

Transistor structure with variable clad/core dimension for stress and bandgap

Disclosed herein are stacked transistors having device strata (130-1, 130-2) with different channel widths (136-1, 136-2), as well as related methods and devices. In some embodiments, an integrated circuit structure (100) may include stacked strata of transistors, wherein different channel materials (106-1, 106-2) of different strata have different widths.

Stacked transistors having device strata with different channel widths

An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Apparatus comprising semiconductor device, method for forming semiconductor device and computing system

An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed.

Stacked transistor layout

FIELD: physics.SUBSTANCE: electronic device ribs are formed by the epitaxial growth of the first material layer over the substrate surface at the gap bottom formed between the side walls of the shallow trench isolation (STI) areas. The trench height may be, at least, 1.5 of its width size, and the first layer may fill less than the trench height. Then, the second material layer may be epitaxially grown on the first trench layer and over the upper surfaces of the STI areas. The second layer may have the second width extending over the tench and over the upper surface portions of the STI areas. The second layer may then be structured and etched to form a pair of the electronic device ribs over the upper surface portions of the STI areas, proximally to the trench.EFFECT: invention makes it possible to eliminate crystal defects in the ribs, because of the difference between the constants of the crystal lattices at the boundary of the layer transition.20 cl, 10 dwg

Jack T. Kavalieros

Papers

Transistor structure with variable clad/core dimension for stress and bandgap

Stacked transistors having device strata with different channel widths

Apparatus comprising semiconductor device, method for forming semiconductor device and computing system

Stacked transistor layout

Defect-free device manufacturing on the basis of rib in cross epitaxial overgrowth area