International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Japanese journal of applied physics : JJAP online.

In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

Tunnel Field-Effect Transistor With an L-Shaped Gate

III-nitride light-emitting diodes (LEDs) suffer from a severe efficiency reduction with increasing injection current (droop) Auger recombination is often seen as primary cause of this droop phenomenon The corresponding Auger recombination coefficient C is typically obtained from efficiency measurements using mathematical models However, C coefficients reported for InGaN active layers vary over two orders of magnitude We here investigate this uncertainty and apply successively more accurate models to the same efficiency measurement, thereby revealing the strong sensitivity of the Auger coefficient to quantum well properties such as electron-hole ratio, electric field, and hot carrier escape

On the uncertainty of the Auger recombination coefficient extracted from InGaN/GaN light-emitting diode efficiency droop measurements

Core-shell germanium nanowire (GeNW) is formed with a single-crystalline Ge core and concentric shells of nitride and silicon passivation layer by chemical vapor deposition (CVD), an Al2O3 gate dielectric layer by atomic layer deposition (ALD) and an Al metal surround-gate (SG) shell by isotropic magnetron sputter deposition. Surround gate nanowire field effect transistors (FETs) are then constructed using a novel self-aligned fabrication approach. Individual SG GeNW FETs show improved switching over GeNW FETs with planar gate stacks owing to improved electrostatics. FET devices comprised of multiple quasi-aligned SG GeNWs in parallel are also constructed. Collectively, tens of SG GeNWs afford on-currents exceeding 0.1mA at low source-drain bias voltages. The self-aligned surround gate scheme can be generalized to various semiconductor nanowire materials.

Parallel Core-Shell Metal-Dielectric-Semiconductor Germanium Nanowires for High Current Surround Gate Field Effect Transistors

An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.

Demonstration of L-Shaped Tunnel Field-Effect Transistors

This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and ${10}^{ {4}}~{ \mathrm{\scriptstyle ON}}/{ \mathrm{\scriptstyle OFF}}$ current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ${I}_{D}$ regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.

Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

For the first time, a comprehensive study is done regarding the stability under simultaneous application of light and gate dc bias in amorphous hafnium-indium-zinc-oxide (α-HIZO) thin-film transistors (TFTs). Subthreshold swing (SS) degradation, a negative threshold voltage (Vth) shift, and the occurrence of hump are observed in transfer curves after applying a negative gate bias and light stress. Based on the retention test at room temperature and the hysteresis analysis, it is revealed that all these phenomena result from hole trapping in the gate insulator. Moreover, it is proven that the SS degradation and hump occurrence are mainly attributed to hole trapping in SiO2 at the edge regions along the channel length/width directions and that a negative Vth shift is derived from hole trapping in the gate insulator far from the SiO2/HIZO interface.

Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p+/n+ body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage ( ${V} _{D}$ )-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration.

Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and shortchannel SBTFET .

Jang Hyun Kim

Papers

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique