Showing papers by "Jean-Christophe Crebier published in 2016"

A Gate Driver With Integrated Deadtime Controller

Abstract: Deadtimes are required to avoid simultaneous conduction of high-side and low-side power transistors in half-bridge power converters. During these secure times, free-wheeling current flow generates extra power losses. Very short deadtimes are desired but they cannot be safely set in conventional isolated power converters because of a digital input propagation delay mismatch. A specific deadtime management is introduced in this paper to ensure proper operation of a high-voltage synchronous power converter. A controller integrated in each isolated gate driver secures synchronous switching by detecting the opposite switch turn-off before turn-on. With such a selfswitching technique, very short but safe nonoverlap times can be set. A gate driver has been implemented in a 0.35 μm 20-V CMOS process. The monolithically integrated controller consumes only 140 μA and 0.22 mm2 of silicon area. The proposed local deadtime management has been validated in two synchronous buck converters without external free-wheeling diodes: a 500-W 250-V to 55-V converter based on SiC JFETs and a 30-W 45-V to 10-V converter based on eGaN FETs. In either case, the proposed controller allows a higher efficiency from 10% of the rated load with resulting deadtimes as short as 15 ns.

Design and Implementation of a Highly Integrated Dual Active Bridge Microconverter

Abstract: This paper deals with the design and the implementation of an isolated and highly integrated low voltage, low power microconverter. A dual active-bridge topology is considered as a good candidate for reducing the number of passive elements. The design of a “power die” integrating power inverter legs and their driver circuits is carried out in order to benefit from the high level of integration and to reduce the amount of active components and the volume of the converter. Thus, a microconverter is built for 10 W power supply (5 V/2 A) and is operating at 1 MHz switching frequency. The measured efficiency of the converter is 88% for 6.5 W transferred power and 86% for 8.5 W transferred power without taking into account its control unit. The converter is operating in natural convection, and no cooling system is implemented. Therefore, a power density of 9.9 kW/L is achieved, which is beyond the state of the art of the conventional isolated converters whose power densities are around 1–2 kW/L at the same power level.

CMOS SOI gate driver with integrated optical supply and optical driving for fast power transistors

Abstract: This paper presents the design, characterization and implementation of a gate driver based on optical transfer of both, the gate driver supply and its control signal isolation for high side and very high switching speed power devices. Our technique is based on the full monolithic integration within the CMOS-SOI gate driver IC of the optical receivers for both functions, associated with signal and power conditioning and power device gate charge control sub systems. Design issues are presented based on Xfab, XT0.18 SOI process. Characterizations are analyzed to underline the effectiveness of the proposed approach in the context of high temperature and its immunity to extremely fast switching power devices.

Instrumented chip dedicated to semiconductor temperature measurements in power electronic converters

Abstract: Temperature measurement of semiconductor components is essential, in particular to evaluate performances and to propose health monitoring of power modules. ThermoSensitive Electrical Parameters (TSEPs) are widely used to estimate a representative temperature of these components, mainly in non-operating conditions, different from the real environment of the latter (offline measurements). Nevertheless, some TSEPs may be adapted to online temperature measurements, in operating conditions of power converters. It is however difficult to evaluate the accuracy of those TSEPs. This paper presents an instrumented chip dedicated to estimate the temperature in power electronic modules under functional constraints. Thus, it offers a reliable and robust tool for temperature measurements in power electronic converters. Preliminary results presented in this paper concern the technological process of realization and demonstrate the good functioning of this instrumented chip under power dissipation and switching conditions.

Contributions to dedicated gate driver circuitry for very high switching speed high temperature power devices

Abstract: Based on WBG power devices operating constraints, this paper analyses and presents developments and prototyping of dedicated high side control signal level shifters. Designs take into account temperature, propagation delay deviation and high dv/dt susceptibility to deliver a generic solution able to comply with new device constraints. If silicon technology remains today the unique reliable technical solution, the implementation of gate driver in this technology is becoming very challenging. Delay deviations, signal integrity (duty cycle duration and time location) of prototypes are characterized with respect to temperature as well as dv/dt immunity.

Numerical and Experimental Evaluation of the Microsecond Pulsed Heating Curve Technique Dedicated to Die Interconnection Characterization

Abstract: This paper describes and qualifies a partial thermal impedance measurement technique to evaluate the thermal behavior of the physical layers close to the die in power electronic assemblies. The measurement approach is derived from the pulsed heating curve method; nonetheless, the experimental setup proposed here is fitted for a higher sensitivity analysis of die interconnections due to the extraction of the transient thermal impedance at very high current levels and short heating times. Another advantage of this method is that the cooling efficiency of the system has no impact on the sensitivity of the measurements, which makes it particularly suitable for aging monitoring or in-line manufacturing process control. The method is then implemented with power diodes in order to compare the thermal impedance of two power modules with different solder void repartitions. Experimental results and finite-element simulations show that this method has a very good sensitivity and can, therefore, be used to compare the quality of different die attaches without requiring an efficient power module cooling system.

CMOS gate drivers with integrated optical interfaces for extremely fast power transistors

Abstract: Novel power semiconductor devices such as GaN High Electron Mobility transistors and SiC MOSFET are allowing significant improvements on switching speeds. Currently, gate drivers are one of the main limitations preventing the highest switching speed operation of wide bandgap power transistors. More especially, isolation barriers are limiting the Common-Mode Transient Immunity (CMTI) of dedicated gate drivers. Here, we propose two CMOS gate drivers with integrated optical receivers to transfer both the gate signal and the gate driver supply directly by light. Two technologies are considered, namely bulk 0.18um CMOS and 0.18um SOI CMOS, both having ultra-low propagation delays and pulse width distortions. The proposed optical interconnect with optical fibers allows extreme CMTI values, defined by the packaging and the distance between light emitting devices and the CMOS gate drivers. These integrated CMOS gate drivers will offer the fastest switching speeds for wide bandgap power transistors.

Integrated isolation functions for driving power semiconductor devices

Abstract: This paper presents several innovative solutions in the view of transferring gate signal orders for power semiconductor devices. While considering both monolithic and heterogeneous integration approaches, three different solutions are presented both theoretically and experimentally. The first integration scheme for the required signal insulation unit is based on integrated optical detectors; optical detectors are designed, fabricated and characterized when integrated within vertical power semiconductor devices and within a CMOS gate driver. The DC and AC performances of the first prototypes are compatible with the requirements and specifications for power converters. As a complementary and competitive integration approach, integrated coreless transformers within CMOS gate drivers are designed and characterized. A particular experimental investigation of high frequency coupling is described. A CMOS gate driver containing both a coreless transformer and other necessary functions is applied to a buck...

Towards vertical power device 3D packaging on 8-inch wafer

Abstract: This paper presents a wafer-level fabrication process of 3D power module based on 8-inch wafer devices and 8-inch metallic bulk leadframe. This approach relies on the intermixing of the packaging process with the front-end fabrication of the power devices. The specific processes to obtain functional power devices and the metallic bulk leadframe manufacturing are described in the paper as essential key enablers of this packaging approach.

Mise en place d'un packaging 3D collectif de composants de puissance à structure verticale

Abstract: Nous presentons dans ce papier l'etat d'avancement d'une approche d'assemblage collectif en 3D de modules electroniques de puissance, basee sur des etapes technologiques de fabrication a l'echelle de la plaque (200 mm de diametre dans notre cas). Le concept repose sur l'integration des etapes de packaging dans la fabrication front-end des composants. C'est une demarche globale de conception couplee composant-package. Cela inclut la conception des composants, les interconnexions, la fabrication et l'assemblage de toutes les parties. Les etapes specifiques de fabrication de composants fonctionnels ainsi que celles conduisant a la realisation d'un leadframe metallique sont decrites ici, comme des elements cles de l'approche de packaging collectif de modules de puissance.