This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13- $\mu {\text {m}}~1$ P8M CMOS technology and occupies only $0.0052~{\text {mm}}^{2}$ . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of −10 dBm and 0.1–-2.2 GHz bandwidth (BW), while consuming only 400 $\mu {\text {A}}$ from a 1-V supply.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This paper proposes a new microstrip slow-wave structure. The unit cell comprises a Schiffman section of meander line and a shunt open-circuited stub. No via-holes and ground-plane patterns are required. Simple design formulas can be used to obtain line parameters, such as the characteristic impedance and phase velocity. According to the analysis, the characteristic impedance and slow-wave factor of the proposed slow-wave line can be independently controlled by merely two layout parameters. The proposed uniplanar structure only requires a single-layer substrate and is simply constructed using the conventional printed circuit board manufacturing process. A branch-line and a rat-race coupler were designed and fabricated using the proposed structure to demonstrate its feasibility. Their sizes are only 8.49% and 4.87% of the conventional ones, respectively. This novel slow-wave structure should find wide applications in compact microwave circuits.

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A High Slow-Wave Factor Microstrip Structure With Simple Design Formulas and Its Application to Microwave Circuit Design

A fully integrated low-dropout-regulated step-down multiphase-switched-capacitor DC–DC converter (a.k.a. charge pump, CP) with a fast-response adaptive-phase (Fast-RAP) digital controller is designed using a 65-nm CMOS process. Different from conventional designs, a low-dropout regulator (LDO) with an NMOS power stage is used without the need for an additional step-up CP for driving. A clock tripler and a pulse divider are proposed to enable the Fast-RAP control. As the Fast-RAP digital controller is designed to be able to respond faster than the cascaded linear regulator, transient response will not be affected by the adaptive scheme. Thus, light-load efficiency is improved without sacrificing the response time. When the CP operates at 90 MHz with 80.3% CP efficiency, only small ripples would appear on the CP output with the 18-phase interleaving scheme, and be further attenuated at $V_{{\rm OUT}}$ by the 50-mV dropout regulator with only 4.1% efficiency overhead and 6.5% area overhead. The output ripple is less than 2 mV for a load current of 20 mA.

An NMOS-LDO Regulated Switched-Capacitor DC–DC Converter With Fast-Response Adaptive-Phase Digital Control

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several g m -enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP 3 is ―12 dBm for an input compression point of —21 dBm.

A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 μm CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $\mu$ m CMOS Process

The effects of RF hot-carrier stress on the characteristics of 60-GHz power amplifiers (PAs) on a CMOS 65-nm process are investigated, for the first time, in this letter. A reliability study is made on a one-stage PA to validate an aging model and the degradation explanation. A drop of 16% of the gain, 17% of the 1-dB output compression point (OCP1 dB), and 17% of the Psat are measured at 60 GHz after 50 h of stress under Vdd = 1.65 V with Pin = 0 dBm and Vdd = 1.9 V with Pin = -10 dBm at 60-GHz frequency.

Hot-Carrier Stress Effect on a CMOS 65-nm 60-GHz One-Stage Power Amplifier

High-performance integrated slow-wave coplanar waveguides (S-CPW) are compared with conventional coplanar waveguides (CPW) fabricated in a 65-nm High-Resistivity-SOI (HR-SOI) CMOS technology. As expected, S-CPW demonstrates better performance at millimeter-wave frequencies in term of higher effective dielectric permittivity, which is due to the patterned floating shield inserted between the transmission line and the substrate. In addition, S-CPW shows a lower attenuation constant despite of the added metallic patterned floating shield on HR substrate. For demonstration purpose, both low- and high- characteristic impedance S-CPW and CPW are characterized. For 28-Ω S-CPW and 65-Ω S-CPW, the effective dielectric permittivity is improved by a factor of 6 and 2, respectively. Meanwhile, attenuation constants of slow-wave structures are lower than 0.9 dB/mm and 0.57 dB/mm at 60 GHz, compared to CPW ones which are as high as 1.5 dB/mm and 0.95 dB/mm, respectively. Furthermore, the loss distribution for the S-CPW structure is detailed by varying the patterned floating shield length for both standard Bulk and HR-SOI substrates.

Performance Improvement Versus CPW and Loss Distribution Analysis of Slow-Wave CPW in 65 nm HR-SOI CMOS Technology

An improved analytical model of the CMOS 65-, 45-, and 32-nm silicon technology integrated transmission line is proposed. This model is derived from previous classical ones used for printed circuits board lines. Improvements have been performed to take into account the size of integrated lines. The study is validated up to millimeter-wave frequencies for different linewidths realized with various metal levels. Accurate results allow the model to be implemented in commercial computer-aided design software commonly used for millimeter-wave designs. A comparison with commercial tools is carried out.

Jean-Michel Fournier

Papers

A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $\mu$ m CMOS Process

Hot-Carrier Stress Effect on a CMOS 65-nm 60-GHz One-Stage Power Amplifier

Performance Improvement Versus CPW and Loss Distribution Analysis of Slow-Wave CPW in 65 nm HR-SOI CMOS Technology

65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies