J
Jean-Michel Fournier
Researcher at Los Angeles Harbor College
Publications - 48
Citations - 467
Jean-Michel Fournier is an academic researcher from Los Angeles Harbor College. The author has contributed to research in topics: CMOS & Amplifier. The author has an hindex of 10, co-authored 46 publications receiving 424 citations. Previous affiliations of Jean-Michel Fournier include University of Grenoble.
Papers
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Proceedings Article
A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS
TL;DR: This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications that provides a high gain and reduced Noise Figure (NF) in spite of the low intrinsic g m of the MOS transistors.
Journal ArticleDOI
High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $\mu$ m CMOS Process
Darine Kaddour,H. Issa,Anne-Laure Franc,N. Corrao,Emmanuel Pistono,Florence Podevin,Jean-Michel Fournier,J.-M. Duchamp,Philippe Ferrari +8 more
TL;DR: In this article, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 μm CMOS technology are provided.
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Hot-Carrier Stress Effect on a CMOS 65-nm 60-GHz One-Stage Power Amplifier
Thomas Quemerais,L. Moquillon,Vincent Huard,Jean-Michel Fournier,Philippe Benech,N. Corrao,Xavier Mescot +6 more
TL;DR: In this paper, the effects of RF hot-carrier stress on the characteristics of 60 GHz power amplifiers on a CMOS 65nm process are investigated, for the first time, in a reliability study.
Journal ArticleDOI
Performance Improvement Versus CPW and Loss Distribution Analysis of Slow-Wave CPW in 65 nm HR-SOI CMOS Technology
Xiao-Lan Tang,A-L Franc,Emmanuel Pistono,Alexandre Siligaris,P. Vincent,Philippe Ferrari,Jean-Michel Fournier +6 more
TL;DR: In this paper, high performance integrated slow-wave coplanar waveguides (S-CPW) are compared with conventional CPW fabricated in a 65-nm High-Resistivity-SOI (HR-SoI) CMOS technology.
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65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies
TL;DR: In this paper, an improved analytical model of the CMOS 65-, 45-, and 32-nm silicon technology integrated transmission line is proposed, which is derived from previous classical ones used for printed circuits board lines.