Jinwook Oh

TL;DR: In the proposed hardware architecture, three recognition tasks (visual perception, descriptor generation, and object decision) are directly mapped to the neural perception engine, 16 SIMD processors including 128 processing elements, and decision processor and executed in the pipeline to maximize throughput of the object recognition.

TL;DR: A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers by employing a dataflow architecture and an on-chip scratchpad hierarchy.

TL;DR: A heterogeneous many-core processor is presented that realizes the UVAM algorithm, which incorporates the familiarity map on top of the saliency map for the search of attentive points, to achieve fast and robust object recognition of cluttered video sequences.

TL;DR: It is shown that hot loops in the applications can be perforated by an average of 50% with proportional reduction in execution time, while still producing acceptable quality of results, and that benefits compounded when these techniques are applied concurrently.

TL;DR: In this article, a 4-core AI chip in 7nm EUV technology is presented to exploit cutting-edge algorithmic advances for iso-accurate models in low-precision training and inference to achieve leading-edge power-performance.