Showing papers by "John H. Magerlein published in 2008"
Patent•
IBM1
TL;DR: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar as mentioned in this paper.
Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.
60 citations
Patent•
IBM1
TL;DR: In this paper, an apparatus to reduce a thermal penalty of a 3D die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environments, which is coupled to the substrate in a stacking direction.
Abstract: An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.
52 citations
Patent•
IBM1
TL;DR: In this paper, a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate, and the liquid cooler is mechanically coupled to the package substrate through a metallic stiffener structure.
Abstract: Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
50 citations
Patent•
IBM1
TL;DR: In this paper, an approach and methods for packaging multi-chip modules with liquid cooling modules designed to provide different thermal resistances for effectively conducting heat from various chips with disparate cooling requirements while minimizing mechanical stresses in thermal bonds due to thermal excursions.
Abstract: Apparatus and methods are provided for packaging multi-chip modules with liquid cooling modules designed to provide different thermal resistances for effectively conducting heat from various chips with disparate cooling requirements while minimizing mechanical stresses in thermal bonds due to thermal excursions.
33 citations
Patent•
IBM1
TL;DR: In this article, the authors propose a manifold-based cooling system with a base layer, a cooling layer including at least inlet slot and at least outlet slot for flowing a coolant across a cooling structure including a plurality of staggered fins arranged in rows and columns.
Abstract: A cooler includes a base layer, a cooling layer including at least one inlet slot and at least one outlet slot for flowing a coolant across a cooling structure including a plurality of staggered fins arranged in rows and columns, wherein fins of adjacent columns are staggered, and at least one manifold layer disposed on the cooling layer for flowing the coolant from a cooler inlet to the at least inlet slot and from the at least one outlet slot to a cooler outlet, the at least one manifold layer having a top layer comprising the cooler inlet and the cooler outlet.
19 citations
TL;DR: In this article, the authors used a control voltage high enough to establish metal-metal contact between the signal electrodes while avoiding contact between dielectric-covered actuation electrodes, and showed that the effect of polarization charge appears to be negligible.
Abstract: MEMS switches having separate signal and actuation electrodes with different air gaps are fabricated using a copper-based CMOS interconnect manufacturing process. By using a control voltage high enough to establish metal-metal contact between the signal electrodes while avoiding contact between the dielectric-covered actuation electrodes, dielectric charging appears to be tolerable. By simultaneously measuring the conductance across the signal electrodes and the capacitance across the actuation electrodes, the conductance-force characteristic can be readily monitored and analyzed. For the present switches, the effect of polarization charge appears to be negligible, and dielectric charging is significant only after dielectric contact is made and space charge is injected.
12 citations