Proceedings ArticleDOI
A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
K. von Arnim,Emmanuel Augendre,A.C. Pacha,T. Schulz,K.T. San,Florian Bauer,Axel Nackaerts,Rita Rooyackers,T. Vandeweyer,Bart Degroote,Nadine Collaert,Abhisek Dixit,R. Singanamalla,Weize Xiong,Andrew Marshall,C.R. Cleavelin,K. Schrufer,Malgorzata Jurczak +17 more
- pp 106-107
TLDR
SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration and NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS.Abstract:
This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.read more
Citations
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Proceedings ArticleDOI
Exploring sub-20nm FinFET design with predictive technology models
TL;DR: Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research and PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap.
Journal ArticleDOI
Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications
Navab Singh,K.D. Buddharaju,Sanjeev Kumar Manhas,Ajay Agarwal,S.C. Rustagi,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +7 more
TL;DR: The current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories are reviewed and the challenges and opportunities are outlined.
Journal ArticleDOI
Multi-gate devices for the 32 nm technology node and beyond
Nadine Collaert,A. De Keersgieter,Abhisek Dixit,Isabelle Ferain,Li-Shyue Lai,Damien Lenoble,Abdelkarim Mercha,Axel Nackaerts,Bartek Pawlak,R. Rooyackers,T. Schulz,K.T. San,N.J. Son,M.J.H. van Dal,Peter Verheyen,K. von Arnim,Liesbeth Witters,K. De Meyer,Serge Biesemans,Malgorzata Jurczak +19 more
TL;DR: The suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed and some technological challenges will be addressed.
Proceedings ArticleDOI
Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?
Angada B. Sachid,Roswald Francis,Maryam Shojaei Baghini,Dinesh K. Sharma,K.-H. Bach,R. Mahnkopf,Valipe Ramgopal Rao +6 more
TL;DR: In this paper, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped finFET.
Proceedings ArticleDOI
Multi-gate devices for the 32nm technology node and beyond
Nadine Collaert,A. De Keersgieter,Abhisek Dixit,Isabelle Ferain,L.-S. Lai,Damien Lenoble,Abdelkarim Mercha,Axel Nackaerts,Bartek Pawlak,R. Rooyackers,T. Schulz,K.T. Sar,N.J. Son,M.J.H. van Dal,Peter Verheyen,K. von Arnim,Liesbeth Witters,De Meyer,Serge Biesemans,Malgorzata Jurczak +19 more
TL;DR: The suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed and some technological challenges will be addressed.