This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.

/pdf/analog-circuits-in-ultra-deep-submicron-cmos-1g96qlvoip.pdf

Analog circuits in ultra-deep-submicron CMOS

With the aim of critically assessing the current models for metal ion assisted hydrolytic reaction mechanisms, an updated review of the current understanding of metallohydrolase-catalyzed reactions is presented. Focus is on four systems, purple acid phosphatases (PAPs), Ser/Thr protein phosphatases (PPs), 3′-5′ exonucleases, and 5′-nucleotidases (5′-NTs), which have contributed to major advancement of the understanding of the catalytic mechanisms that operate in such enzymes.

/pdf/the-catalytic-mechanisms-of-binuclear-metallohydrolases-2gxxvk9jno.pdf

The catalytic mechanisms of binuclear metallohydrolases.

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

Foreword. Preface. List of Symbols. 1. Introduction. 1.1 The Importance of Device Modeling for IC Design. 1.2 A Short History of the EKV MOST Model. 1.3 The Book Structure. PART I: THE BASIC LONG-CHANNELINTRINSIC CHARGE-BASED MODEL. 2. Introduction. 2.1 The N-channel Transistor Structure. 2.2 Definition of charges, current, potential and electric fields. 2.3 Transistor symbol and P-channel transistor. 3. The Basic Charge Model. 3.1 Poisson's Equation and Gradual Channel Approximation. 3.2 Surface potential as a Function of Gate Voltage. 3.3 Gate Capacitance. 3.4 Charge Sheet Approximation. 3.5 Density of Mobile Inverted Charge. 3.6 Charge-Potential Linearization. 4. Static Drain Current. 4.1 Drain Current Expression. 4.2 Forward and Reverse Current Components. 4.3 Modes of Operation. 4.4 Model of Drain Current Based on Charge Linearization. 4.5 Fundamental Property: Validity and Application. 4.6 Channel Length Modulation. 5. The Small-Signal Model. 5.1 The Static Small-Signal Model. 5.2 A General Non-Quasi-Static Small-Signal Model. 5.3 The Quasi-Static Dynamic Small-Signal Model. 6. The Noise Model. 6.1 Noise Calculation Methods. 6.2 Low-Frequency Channel Thermal Noise. 6.3 Flicker Noise. 6.4 Appendices. Appendix : The Nyquist and Bode Theorems. Appendix : General Noise Expression. 7. Temperature Effects and Matching. 7.1 Introduction. 7.2 Temperature Effects. PART II: THE EXTENDED CHARGE-BASED MODEL. 8. Non-Ideal Effects Related to the Vertical Dimension. 8.1 Introduction. 8.2 Mobility Reduction Due to the Vertical Field. 8.3 Non-Uniform Vertical Doping. 8.4 Polysilicon Depletion. 8.4.1 Definition of the Effect. 8.5 Band Gap Widening. 8.6 Gate Leakage Current. 9. Short-Channel Effects. 9.1 Velocity Saturation. 9.2 Channel Length Modulation. 9.3 Drain Induced Barrier Lowering. 9.4 Short-Channel Thermal Noise Model. 10. The Extrinsic Model. 10.1 Extrinsic Part of the Device. 10.2 Access Resistances. 10.3 Overlap Regions. 10.4 Source and Drain Junctions. 10.5 Extrinsic Noise Sources. PART III: THE HIGH-FREQUENCY MODEL. 11. Equivalent Circuit at RF. 11.1 RF MOS Transistor Structure and Layout. 11.2 What Changes at RF?. 11.3 Transistor Figures of Merit. 11.4 Equivalent Circuit at RF. 12. The Small-Signal Model at RF. 12.1 The Equivalent Small-Signal Circuit at RF. 12.2 Y-Parameters Analysis. 12.3 The Large-Signal Model at RF. 13. The Noise Model at RF. 13.1 The HF Noise Parameters. 13.2 The High-Frequency Thermal Noise Model. 13.3 HF Noise Parameters of a Common-Source Amplifier. References. Index.

Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design

In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

This paper presents a new parameter extraction methodology, based on an accurate and continuous MOS model dedicated to low-voltage and low-current analog circuit design and simulation (EKV MOST Model). The extraction procedure provides the key parameters from the pinch-off versus gate voltage characteristic, measured at constant current from a device biased in moderate inversion. Unique parameter sets, suitable for statistical analysis, describe the device behavior in all operating regions and over all device geometries. This efficient and simple method is shown to be accurate for both submicron bulk CMOS and fully depleted SOI technologies.

http://epicentertech.com/Research/Device_Modeling/EKV_MOS_Model/EKV_Modeling_Docs/icmts96.pdf

An efficient parameter extraction methodology for the EKV MOST model

The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS, allowing to coherently determine VTH for the entire range of VDS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

A methodology for small signal characterization of CMOS processes over the full range of inversion level and channel length is presented Measured transconductance and output conductance of a 05 /spl mu/m standard CMOS process are presented from deep weak inversion to deep strong inversion for both NMOS and PMOS devices for channel lengths ranging from 05 /spl mu/m to 334 /spl mu/m The data is presented in normalized form permitting device evaluation at any inversion level, channel length, and drain current This characterization is useful for modern analog CMOS design anywhere in the continuum of inversion level and channel length This method furthermore presents a novel and rigorous benchmark for evaluating the accuracy of compact MOS models Initial results are given illustrating EKV MOS model transconductance accuracy The characterization methodology can be extended to deeper submicron processes addressing the increasing uncertainty in small signal parameter values and MOS model accuracy

Matthias Bucher

Papers

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

An efficient parameter extraction methodology for the EKV MOST model

An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

Design-oriented characterization of CMOS over the continuum of inversion level and channel length