S
S.-J. Jeng
Researcher at IBM
Publications - 23
Citations - 1240
S.-J. Jeng is an academic researcher from IBM. The author has contributed to research in topics: Heterojunction bipolar transistor & CMOS. The author has an hindex of 14, co-authored 23 publications receiving 1212 citations.
Papers
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Journal ArticleDOI
Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology
Basanth Jagannathan,Marwan H. Khater,Francois Pagette,Jae-Sung Rieh,David Angell,H. Chen,John E. Florkey,F. Golan,David R. Greenberg,R.A. Groves,S.-J. Jeng,J. Johnson,E. Mengistu,Kathryn T. Schonenberg,C.M. Schnabel,Peter Andrew Smith,Andreas D. Stricker,David C. Ahlgren,Gregory G. Freeman,Kenneth J. Stein,S. Subbanna +20 more
TL;DR: In this paper, a SiGe NPN HBT with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Mason's unilateral gain of 285 GHz was reported.
Proceedings ArticleDOI
SiGe HBTs with cut-off frequency of 350 GHz
Jae-Sung Rieh,Basanth Jagannathan,H. Chen,Kathryn T. Schonenberg,David Angell,Anil K. Chinthakindi,John E. Florkey,F. Golan,David R. Greenberg,S.-J. Jeng,Marwan H. Khater,Francois Pagette,Christopher M. Schnabel,Peter Andrew Smith,Andreas D. Stricker,K. Vaed,Richard P. Volant,David C. Ahlgren,Gregory G. Freeman,K. Stein,Seshadri Subbanna +20 more
TL;DR: In this paper, the SiGe HBTs with f/sub T/ of 350 GHz were reported, which is the highest reported f/Sub T/ for any Si-based transistor as well as any bipolar transistor.
Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Proceedings ArticleDOI
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
Shreesh Narasimha,Katsunori Onishi,Hasan M. Nayfeh,A. Waite,M. Weybright,Jeffrey B. Johnson,Carlos A. Fonseca,D. Corliss,C. Robinson,Michael Crouse,D. Yang,C-H.J. Wu,Allen H. Gabor,Thomas N. Adam,Ishtiaq Ahsan,Michael P. Belyansky,L. Black,Shahid Butt,J. Cheng,Anthony I. Chou,G. Costrini,Christos D. Dimitrakopoulos,Anthony G. Domenicucci,P. Fisher,A. Frye,S. Gates,Stephen E. Greco,Stephan Grunow,M. Hargrove,Judson R. Holt,S.-J. Jeng,M. Kelling,B. Kim,William F. Landers,G. Larosa,D. Lea,Ming-Hsiu Lee,X. Liu,Naftali E. Lustig,A. McKnight,L. Nicholson,D. Nielsen,Karen A. Nummy,Viorel Ontalus,C. Ouyang,X. Ouyang,C. Prindle,R. Pal,Werner A. Rausch,D. Restaino,Christopher D. Sheraw,J. Sim,Andrew H. Simon,Theodorus E. Standaert,Chun-Yung Sung,Keith H. Tabakman,C. Tian,R. Van Den Nieuwenhuizen,H. van Meer,A. Vayshenker,Deepal Wehella-Gamage,J. Werking,R. C. Wong,S. Wu J. Yu,R. Augur,D. Brown,X. Chen,Daniel C. Edelstein,A. Grill,Mukesh Khare,Yujun Li,S. Luning,J. Norum,Sujatha Sankaran,Dominic J. Schepis,Richard A. Wachnik,Richard Wise,C. Wann,T. Ivers,Paul D. Agnello +79 more
TL;DR: In this paper, the authors present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay.
Journal ArticleDOI
A 210-GHz f/sub T/ SiGe HBT with a non-self-aligned structure
S.-J. Jeng,Basanth Jagannathan,Jae-Sung Rieh,J. Johnson,Kathryn T. Schonenberg,David R. Greenberg,Andreas D. Stricker,H. Chen,Marwan H. Khater,David C. Ahlgren,Gregory G. Freeman,Kenneth J. Stein,S. Subbanna +12 more
TL;DR: In this paper, a 210 GHz f/sub T/SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA/spl mu/m/sup 2/ is fabricated with a new non-self-aligned (NSA) structure based on 0.18 /spl µ/m technology.