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Showing papers by "Pragya Kushwaha published in 2017"


Journal ArticleDOI
TL;DR: In this paper, the authors present a compact model for source-to-drain tunneling current in sub-10nm gate-all-around FinFETs, which analytically captures the dependence on biases in the tunneling probability expression.
Abstract: We present a compact model for source-to-drain tunneling current in sub-10-nm gate-all-around FinFET, where tunneling current becomes nonnegligible. Wentzel–Kramers–Brillouin method with a quadratic potential energy profile is used to analytically capture the dependence on biases in the tunneling probability expression and simplify the equation. The calculated tunneling probability increases with smaller effective mass and with increasing bias. We at first use the Gaussian quadrature method to integrate Landauer’s equation for tunneling current computation without further approximations. To boost simulation speed, some approximations are made. The simplified equation shows a good accuracy and has more flexibility for compact model purpose. The model is implemented into industry standard Berkeley Short-channel IGFET Model-common multi-gate model for future technology node, and is validated by the full-band atomistic quantum transport simulation data.

15 citations


Journal ArticleDOI
TL;DR: In this paper, an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs is presented.
Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

14 citations


Journal ArticleDOI
TL;DR: In this paper, the back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed.
Abstract: The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

13 citations


Proceedings ArticleDOI
01 Oct 2017
TL;DR: This paper has characterized 14-nm N-channel bulk FinFETs by performing two-port S-parameter measurements and BSIM-CMG model for common multiple gate devices is used to accurately capture the RF behavior of the device.
Abstract: RF CMOS technology provides a platform for the production of analog, digital and RF circuits on a single chip for futuristic high-level integration. This facilitates the need for a robust compact model for RF FinFETs to study the circuits in a precise and convenient way. In this paper, we have characterized 14-nm N-channel bulk FinFETs by performing two-port S-parameter measurements. Further, BSIM-CMG model for common multiple gate devices is used to accurately capture the RF behavior of the device.

3 citations


Proceedings ArticleDOI
01 Apr 2017
TL;DR: In this paper, the authors have reported an increase in small signal trans-conductance (g m ) with increase in frequency because of this coupling, which is modulated by changing the substrate doping and BOX thickness.
Abstract: The continuous reduction in the thickness of body and BOX of FDSOI MOS devices (to sustain scaling) have resulted in increased coupling between the top-gate and substrate underneath BOX. In this work, we have reported an increase in small signal trans-conductance (g m ) with increase in frequency because of this coupling. This dependence is modulated by changing the substrate doping and BOX thickness. The physical mechanism responsible for this behavior is explained through measurement on different test structures and detailed device simulation.

2 citations