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Rafal Kleczek

Researcher at AGH University of Science and Technology

Publications -  46
Citations -  715

Rafal Kleczek is an academic researcher from AGH University of Science and Technology. The author has contributed to research in topics: Detector & CMOS. The author has an hindex of 9, co-authored 41 publications receiving 583 citations.

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Journal ArticleDOI

Challenges in QCD matter physics --The scientific programme of the Compressed Baryonic Matter experiment at FAIR

T. O. Ablyazimov, +602 more
TL;DR: The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates.
Journal ArticleDOI

Challenges in QCD matter physics - The Compressed Baryonic Matter experiment at FAIR

T. O. Ablyazimov, +586 more
TL;DR: The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates as discussed by the authors.
Journal ArticleDOI

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

TL;DR: In this article, a prototype integrated circuit built in a 40-nm CMOS process for readout of a hybrid pixel detector is presented, which is designed to operate in both the standard single photon counting mode and the single-photon counting mode with interpixel communication to mitigate negative effects of charge sharing.
Journal ArticleDOI

Characterization of the STS/MUCH-XYTER2, a 128-channel time and amplitude measurement IC for gas and silicon microstrip sensors

TL;DR: The STS/MUCH-XYTER2 (or SMX2) is a 128-channel prototype ASIC for silicon strip detectors and gas electron multiplier (GEM) detectors in the Compressed Baryonic Matter (CBM) experiment as mentioned in this paper.
Proceedings ArticleDOI

A bidirectional 64-channel neurochip for recording and stimulation neural network activity

TL;DR: In this paper, the authors present a 64 channel ASIC dedicated for recording and stimulation of neural network activity, which is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel.