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Journal ArticleDOI

Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects

TLDR
Pretet et al. as discussed by the authors investigated the super-coupling effect in fully depleted SOI devices and revealed new challenges in the characterization of ultra-thin devices, such as gate oxide tunneling, thin buried oxide, and ultra thin films.
Abstract
A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices.

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Citations
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Journal ArticleDOI

A Review of Sharp-Switching Devices for Ultra-Low Power Applications

TL;DR: In this article, a review of CMOS-compatible devices capable of switching more abruptly than MOSFETs, and discuss their merits and limitations is presented. But the authors do not consider the effect of channel materials and geometries.
Journal ArticleDOI

Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in Ultra-Thin-Body

TL;DR: The UTB DGISFET will allow the ISFET-based biosensor platform to continue enhancement into the next decade and provide a comprehensive analysis of the body thickness effects especially how the thick body can render the degradation in the device performance, such as sensitivity and stability.
Journal ArticleDOI

Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates

TL;DR: In this paper, a multibody single-transistor dynamic-random-access-memory (DRAM) cell based on the juxtaposition of two silicon films with opposed doping polarities (i.e., a p-n junction) is presented.

Performance Enhancement of Capacitive-Coupling Dual-gate Ion-Sensitive Field-Effect Transistor in

TL;DR: In this article, the authors embedded the ultra-thin body (UTB) into the dual-gate (DG) structure of a thin-film transistor based-ISFET to increase its sensitivity and suppress the leakage components.
Journal ArticleDOI

Impact of free surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization

TL;DR: Hovel et al. as mentioned in this paper investigated the influence of top free-surface states on the pseudo-MOSFET characteristics by comparing passivated versus nonpassivated samples, and the parameters of concern, investigated here, are carrier mobility, density of interface states, threshold (VT), and flatband (VFB) voltages.
References
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Book

Operation and modeling of the MOS transistor

TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Journal ArticleDOI

Frontiers of silicon-on-insulator

TL;DR: In this article, the authors discuss methods of forming silicon-on-insulator (SOI) wafers, their physical properties, and the latest improvements in controlling the structure parameters.
Journal ArticleDOI

Threshold voltage of thin-film Silicon-on-insulator (SOI) MOSFET's

TL;DR: In this article, the charge coupling between the front and back gates of thin-film silicon-on-insulator (SOI) MOSFETs is analyzed, and closed-form expressions for the threshold voltage under all possible steady-state conditions are derived.
Book

Electrical Characterization of Silicon-on-Insulator Materials and Devices

Abstract: 1. Introduction. 2. Methods of Forming SOI Wafers. 3. SOI Devices. 4. Wafer Screening Techniques. 5. Transport Measurements. 6. SUS Capacitor Based Characterization Techniques. 7. Diode Measurements. 8. Transistor Characteristics. 9. Transistor Based Characterization Techniques. 10. Monitoring the Transistor Degradation. Index.
Journal ArticleDOI

Correct biasing rules for virtual DG mode operation in SOI-MOSFETs

TL;DR: In this article, the appropriate biasing rules for virtual double-gate (DG) operation of silicon-on-insulator (SOI)-MOSFETs are investigated and the cause for the optimistic subthreshold swing, achieved by the conventional biasing rule, is discussed and a correct methodology is proposed.
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