Showing papers by "Robert Bogdan Staszewski published in 2005"

All-digital PLL and transmitter for mobile phones

Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

Phase-domain all-digital phase-locked loop

Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump-based phase-locked loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. An actual implementation of an all-digital PLL (ADPLL)-based local oscillator and transmitter used in a commercial 0.13-/spl mu/m CMOS single-chip Bluetooth radio has recently been disclosed. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. Due to the lack of the correlational phase detection mechanism, the loop does not contribute to the reference spurs. The measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications. In this paper, we present the mathematical description and operational details of the phase-domain ADPLL.

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

Abstract: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

Hybrid polar/cartesian digital modulator

Abstract: A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

Abstract: We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.

Method and apparatus for a fully digital quadrature modulator

Abstract: A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

Event-driven Simulation and modeling of phase noise of an RF oscillator

Abstract: A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.

Digital RF processing: toward low-cost reconfigurable radios

Abstract: RF circuits for multi-gigahertz frequencies have recently migrated to state-of-the-art low-cost digital CMOS processes. This article visits fundamental techniques recently developed that migrate RF and analog design complexity to the digital domain for a wireless RF transceiver. All-digital phase locked loop and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software-defined radio. The ideas presented have been used to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

Circuit for high-resolution phase detection in a digital RF processor

Abstract: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

Gain calibration of a digital controlled oscillator

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS

Abstract: We present the first 90-nm digital CMOS RF power amplifier. This PA contains a large array of NMOS switches, and performs a direct digital-to-RF-amplitude conversion, filtering and buffering in a fully-integrated GSM/EDGE transmitter. Power control is fully digital. 40% efficiency is obtained at 10-dBm output power from 1.4 V and it occupies 0.005 mm/sup 2/.

A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process

Abstract: We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive chain uses discrete-time analog signal processing to down convert, down- sample, filter and analog-to-digital convert the received signal. An auxiliary feedback is provided at the mixer output that can linearize the entire receive chain. The receiver meets a sensitivity of -110 dBm at 60 mA in a 1.4V digital CMOS process

Time-to-digital converter for RF frequency synthesis in 90 nm CMOS

Abstract: We propose and demonstrate a 20 ps time-to-digital converter (TDC) in 90 nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital architecture that makes it insensitive to NMOS and PMOS mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with estimation accuracy better than 1%. Measured INL is 0.7 LSB. The TDC consumes 1.3 mA from a 1.3 V supply.

Apparatus for and method of noise suppression and dithering to improve resolution quality in a digital RF processor

Abstract: A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.

Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator

Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination

Abstract: We propose and demonstrate a Gaussian frequency-shift keying and Gaussian minimum-shift keying (GMSK) pulse-shape filtering for wireless RF transmitters with an arbitrary reference frequency. The filter is software controlled to work in a multistandard radio. Spurs, which are due to the frequency injection pulling, in cases when the reference harmonics are close enough to the oscillating frequency, are avoided by means of retiming the reference clock by the RF oscillator. Baseband clock for the pulse-shape filtering is derived through a simple fractional-N division of the reference frequency. This saves area and power since it is no longer required to create a low-jitter clock for baseband symbol generation and modulating data. It is especially advantageous when the available reference frequency is not an integer multiple of the symbol rate. The presented transmitter is realized without any explicit analog filtering and is part of a commercial single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. We demonstrate the software programming capability through an experimental GMSK modulation for the global system for mobile communication.

Image reject filtering in a direct sampling mixer

Abstract: Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Rotation of a switched capacitor CR between the I and Q channels of the circuit causes a sharing of the charge among the four paths, I+, I-, Q+, Q-, resulting in a direct sampling and a complex filtering arrangement (10). The preferred embodiment of the filter (10) shown can be seen to have four sub-circuits (12, 14, 16, 18), which may be understood as single-pole IIR filters. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.

Digital RF processor (DRP/spl trade/) for cellular phones

Abstract: RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and HF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct HF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software defined radio. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

All-Digital PLL with Ultra Fast Acquisition

Abstract: A fully-digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally-controlled oscillator that deliberately avoids any analog tuning controls. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in a digital deep-submicron CMOS process, the proposed architecture is more advantageous over conventional charge-pump-based PLL's since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this paper, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of les50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in 130-nm CMOS

A first RF digitally-controlled oscillator for mobile phones

Abstract: We propose and demonstrate the first RF digitally-controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip fully-compliant quad-band GSM transceiver realized in a 90 nm digital CMOS process. Frequency tuning is achieved through digital control of an array of standard n-poly/n-well MOSCAP devices. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. We analyze the effect of high-speed varactor dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the dithering.

SoC with an integrated DSP and a 2.4-GHz RF transmitter

Abstract: We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

Low noise high isolation transmit buffer gain control mechanism

Abstract: A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.

A first RF digitally-controlled oscillator for SAW-less TX in cellular systems

Abstract: A first digitally-controlled oscillator for mobile stations is presented. Combining a MTM capacitor and two NMOS transistor arrays for the varactor as an RF DAC, a highly linear oscillator gain is achieved, and is insensitive to process shift. With a sigma-delta dithering, a fine frequency resolution is obtained while having negligible phase noise degradation. The measured -167dBc/Hz at 20MHz offset from 915MHz carrier proves that this DCO system can be used in a SAWless transmitter for mobile phones.

Phase-Domain All-Digital Phase-Locked Loop

Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump-based phase-locked loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits An actual implementation of an all-digital PLL (ADPLL)-based local oscillator and transmitter used in a commercial 013-/spl mu/m CMOS single-chip Bluetooth radio has recently been disclosed The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter Due to the lack of the correlational phase detection mechanism, the loop does not contribute to the reference spurs The measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications In this paper, we present the mathematical description and operational details of the phase-domain ADPLL

Digital RF Processor (DRP™) for Cellular Radios

Abstract: RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

Built-in self testing (BIST) of RF performance in a system-on-chip (SoC)

Abstract: The advantages of having an on-chip system for measuring critical RF performance parameters are endless With this capability, millions of ICs can be tested using a low cost tester while benefiting from an increase in test coverage and a reduction in test time and cost in a production environment Another significant benefit is in the factory calibration procedures of critical device settings before deployment Finally, this capability can allow the wireless terminal to periodically log performance results in flash memory from which they can be retrieved during the repair of a damaged unit easing debug analysis by the manufacturer This paper presents a novel method of executing on-chip low-cost performance and compliance testing of a local oscillator and transmitter in a wireless transceiver The presented techniques have been implemented and successfully tested in a Texas Instruments commercial 130 nm CMOS single-chip Bluetooth radio and are being redefined for the 90nm single-chip GSM radio

Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator

Abstract: The use of deep sub-micron CMOS processes presents several daunting challenges to the RF designers. The latest CMOS technologies, optimized for parameters suited to digital designs only, are forcing the analog and mixed-signal designers to make multi-dimensional trade-offs. In general, the lack of adequate analog device characterization and inaccurate SPICE models mandate several expensive additional design and fabrication iterations before arriving at an acceptable solution. Sometimes, the task is further complicated by the difficulty in even making reliable lab measurements due to accuracy issues caused by probing noise, minuscule device sizing, dynamic effects and loading. This paper summarizes the harmonic characterization techniques used to estimate the mismatches in the minimal size inversion-type CMOS varactors in a digitally controlled oscillator (DCO). The DCO is a centerpiece of the first ever all-digital phase locked loop (ADPLL) fabricated in 90 nm digital CMOS that meets the challenging GSM performance specifications. Simulation as well as lab measurements confirm that the tracking bank varactors have a better than 5.5% mismatch, thus contributing to the excellent modulation performance.

Method and apparatus for crystal drift compensation

Abstract: A mobile device includes frequency synthesizer circuitry (44) for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator (72), without frequency stabilization circuitry. Variations in the output of the crystal oscillator (72) are compensated by adjusting the multiplication factor of the frequency synthesizer.

A GSM/GPRS receiver front-end with discrete-time filters in a 90 nm digital CMOS

Abstract: An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90 nm digital CMOS technology is presented The circuit consisting of low noise amplifier, transconductance amplifier and switching mixer, offers 325 dB dynamic range with digitally-configurable voltage gain of 40 dB down to 75 dB A series of decimation and discrete-time filtering follows the mixer and performs a highly-linear second-order low-pass filtering to reject close-in interferers The front-end gains can be configured with an automatic-gain-control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations Even under the digital switching activity, noise figure at the 40 dB maximum gain is 18 dB and +50 dBm IIP/sub 2/ at the 34 dB gain The variation of the input matching versus multiple gains is less than 1 dB The circuit in total occupies 31 mm/sup 2/ The LNA, TA and mixer consume less than 153 mA at a supply voltage of 14 V

Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

Abstract: In this paper, we describe a new architecture of high-speed multibit /spl Sigma//spl Delta/ noise shaping for digital-to-frequency conversion (DFC) and digital-to-RF-amplitude conversion (DRAC). The DFC and DRAC are instrumental in performing phase modulation (PM) and amplitude modulation (AM) of an RF polar transmitter. Since current biasing and continuous-time analog filtering of a conventional transmit modulator are avoided in this all-digital architecture, it is amenable to large-scale integration in an SoC realized in a digital deep-submicron CMOS process. The approach is demonstrated in the first single-chip fully-compliant GSM/EDGE transceiver realized in 90-nm CMOS.