BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this paper, we propose to bring aging awareness to EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on both threshold voltage (V th ) and carrier mobility (μ) of transistors. This is unlike state of the art which considers V th only. We show how ignoring s degradation leads to underestimating guard-bands by 19% on average. Our investigation revealed that the impact of aging is strongly dependent on the operating conditions of gates (i.e. input signal slew and output load capacitance), and not solely on the duty cycle of transistors. Neglecting this fact results in employing insufficient guard-bands and thus not sustaining reliability during lifetime. We demonstrate that degradation-aware libraries and tool flows are indispensable for not only accurately estimating guardbands, but also efficiently containing them. By considering aging degradations during logic synthesis, significantly more resilient circuits can be obtained. We further quantify the impact of aging on the degradation of image processing circuits. This goes far beyond investigating aging with respect to path delays solely. We show that in a standard design without any guardbanding, aging leads to unacceptable image quality after just one year. By contrast, if the synthesis tool is provided with the degradation-aware cell library, high image quality is sustained for 10 years (even under worst-case aging and without a guardband). Hence, using our approach, aging can be effectively suppressed.

Reliability-aware design to suppress aging

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems. Designing efficient, scalable and low-thermal-budget 2D Materials for 3D integration remains a challenge. Here, the authors report the development of a hybrid-(solution-processed-exfoliated) integration of 2D Material based 1T1R which uses a multilayer WSe2 p-FET and a multilayer printed WSe2 RRAM.

/pdf/all-wse2-1t1r-resistive-ram-cell-for-future-monolithic-3d-4cc2tnuavq.pdf

All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration.

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

With technology in deep nano scale, the susceptibility of transistors to various aging mechanisms such as Negative/ Positive Bias Temperature Instability (NBTI/PBTI) and Hot Carrier Induced Degradation (HCID) etc. is increasing. As a matter of fact, different aging mechanisms simultaneously occur in the gate dielectric of a transistor. In addition, scaling in conjunction with high-K materials has made aging mechanisms, that have often been assumed to be negligible (e.g., PBTI in NMOS and HCID in PMOS), become noticeable. Therefore, in this paper we investigate the key challenge of providing designers with an abstracted, yet accurate reliability estimation that combines, from the physical to system level, the effects of multiple simultaneous aging mechanisms and their interdependencies. We show that the overall aging can be modeled as a superposition of the interdependent aging effects. Our presented model deviates by around 6% from recent industrial physical measurements. We conclude from our experiments that an isolated treatment of individual aging mechanisms is insufficient to devise effective mitigation strategies in current and upcoming technology nodes. We also demonstrate that estimating reliability due to an individual dominant aging mechanism together with solely considering a single kind of failures, as currently is a main focus of state-of-the-art (e.g., [28], [22]), can result in 75% underestimation on average.

Towards interdependencies of aging mechanisms

BSIM compact models have served industry for more than a decade starting with BSIM3 and later BSIM4 and BSIMSOI. Here we will briefly discuss the ongoing work on current and future device models in BSIM group. BSIM6 is the next generation bulk RF MOSFET Model which uses charge based core with physical models adapted from BSIM4. Model fulfills all symmetry tests and shows correct slopes for harmonics. The BSIM-CMG and BSIM-IMG are the surface potential based models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Models include all read device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.

BSIM — Industry standard compact MOSFET models

Continuous technology advancements have forced MOSFET architecture to evolve from bulk to SOI to multigate MOSFETs. BSIM compact models have helped circuit designers to realize their designs first time correct using accurate physical models used in SPICE simulation. BSIM3 and BSIM4 are threshold voltage based bulk MOSFET models while BSIM6 is charge based bulk MOSFET model, which include physical effects such as mobility degradation, current saturation, high frequency models etc. BSIM6 has been developed especially to address symmetry around Vds = 0, thus providing smooth higher order derivatives. BSIM-CMG is a CMC standard surface potential based model for common symmetric double, triple, quadruple and surround gate (nanowire) MOSFETs. Long channel DIBL also called Drain-Induced Threshold Shift (DITS) effect and asymmetric charge weighing factor etc. have been recently included in it. BSIM-IMG is a surface potential based model to simulate ultra-thin body devices such as UTBSOI but also other thin body devices such as MOS2 transistor.

BSIM compact MOSFET models for SPICE simulation

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

FinFET and UTBSOI (or ETSOI) FET are the two promising multi-gate FET candidates for sub-22nm CMOS technology. The BSIM-CMG and BSIM-IMG are the surface potential based physical compact models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Both models have been verified by simulation /measurements and show excellent results for all types of real device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.

Compact models for sub-22nm MOSFETs

We present an efficient approach to model the effects of vertical non-uniform doping in bulk MOSFETs. The impact of vertical non-uniform doping on device characteristics is analyzed through systematic TCAD simulations. The qualitative nature of the observed effects is also confirmed by the experimental data available in the literature. A modeling methodology for these effects is developed on BSIM6 model framework. The proposed model is in good agreement with the TCAD simulations.

S. Venugopalan

Papers

BSIM — Industry standard compact MOSFET models

BSIM compact MOSFET models for SPICE simulation

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

Compact models for sub-22nm MOSFETs

Analysis and modeling of vertical non-uniform doping in bulk MOSFETs for circuit simulation