Proceedings ArticleDOI
Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations
S. Venugopalan,Yogesh Singh Chauhan,Darsen D. Lu,M. A. Karim,Ali M. Niknejad,Chenming Hu +5 more
- pp 1-4
TLDR
In this paper, the authors identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics in a vertical cylindrical gate transistor.Abstract:
In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.read more
Citations
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Proceedings ArticleDOI
BSIM — Industry standard compact MOSFET models
Yogesh Singh Chauhan,S. Venugopalan,Mohammed A. Karim,Sourabh Khandelwal,Navid Paydavosi,P. K. Thakur,Ali M. Niknejad,Chenming Hu +7 more
TL;DR: The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFETs as discussed by the authors, which is the surface potential based model for multi-gate MOSFs.
Patent
Method for Inducing Strain in Vertical Semiconductor Columns
TL;DR: In this article, a vertical metal-oxide-semiconductor (MOS) transistor with a gate dielectric encircling a portion of the nano-wire is described.
Patent
Inducing localized strain in vertical nanowire transistors
TL;DR: In this paper, the authors propose a device consisting of a semiconductor substrate and a vertical nano-wire over the semiconductor substrategies, which includes a bottom source/drain region, a channel region over the bottom source and drain regions over the channel region, and a top source/drain region over channel region.
Patent
Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
TL;DR: In this paper, the authors describe a semiconductor device with a substrate, a first source/drain contact region, a channel structure, a gate dielectric, and a gate electrode.
Journal ArticleDOI
Modeling of nonlinear thermal resistance in FinFETs
Bala Krishna Kompala,Pragya Kushwaha,Harshit Agarwal,Sourabh Khandelwal,Juan Pablo Duarte,Chenming Hu,Yogesh Singh Chauhan +6 more
TL;DR: In this paper, the authors investigated the thermal resistance of FinFETs with the variation in the number of fin, shape of fin and fin pitch, and proposed a model for thermal resistance behavior correctly with N fin and F pitch variation.
References
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Proceedings ArticleDOI
Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application
Sung-Jin Whang,Ki-hong Lee,Dae-Gyu Shin,Beom-Yong Kim,MinSoo Kim,JinHo Bin,Ji-Hye Han,Kim Sungjun,BoMi Lee,Young-Kyun Jung,Sung-Yoon Cho,ChangHee Shin,Hyun-Seung Yoo,SangMoo Choi,Kwon Hong,Seiichi Aritome,Sungki Park,Sung-Joo Hong +17 more
TL;DR: In this article, a 3D dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell has been successfully developed, which consists of a surrounding floating gate with stacked dual control gate.
Proceedings ArticleDOI
BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design
Mohan Dunga,Chung-Hsun Lin,Darsen D. Lu,Weize Xiong,C.R. Cleavelin,P. Patruno,Jiunn-Ren Hwang,Fu-Liang Yang,Ali M. Niknejad,Chenming Hu +9 more
TL;DR: In this article, a novel surface potential based multi-gate FET (MG-FET) compact model has been developed for mixed-signal design applications, where the expressions for terminal currents and charges are co-continuous making the model suitable for mixed signal design.
Journal ArticleDOI
Vertical-Si-Nanowire-Based Nonvolatile Memory Devices With Improved Performance and Reduced Process Complexity
Y. Sun,H. Y. Yu,Navab Singh,K. C. Leong,Elena Gnani,Giorgio Baccarani,G. Q. Lo,Dim-Lee Kwong +7 more
TL;DR: In this article, a gate-all-around nonvolatile memory (NVM) device of two different kinds: junction based and junctionless (JL) Si nanocrystals (SiNCs) and silicon nitride (SiN) are used as trap layers.
Proceedings ArticleDOI
BSIM-CG: A compact model of cylindrical gate / nanowire MOSFETs for circuit simulations
V. Sriramkumar,Darsen D. Lu,Tanvir Morshed,Yukiya Kawakami,Peter M. Lee,Ali M. Niknejad,Chenming Hu +6 more
TL;DR: In this paper, a full-fledged surface potential based compact model for cylindrical gate transistors with physical effects such as polysilicon gate depletion, mobility degradation, quantum mechanical effects, short channel effects, leakage currents, and parasitic resistances and capacitances etc.