Open Access
Compact models for sub-22nm MOSFETs
Yogesh Singh Chauhan,Darsen D. Lu,S. Venugopalan,M. A. Karim,Ali M. Niknejad,Chenming Hu +5 more
- pp 720-725
TLDR
The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFETs for sub-22nm CMOS technology.Abstract:
FinFET and UTBSOI (or ETSOI) FET are the two promising multi-gate FET candidates for sub-22nm CMOS technology. The BSIM-CMG and BSIM-IMG are the surface potential based physical compact models for multi-gate MOSFETs. The BSIM-CMG model has been developed to model common symmetric double, triple, quadruple and surround gate MOSFET. The BSIM-IMG model has been developed to model independent double-gate MOSFET capturing threshold voltage variation with back gate bias. Both models have been verified by simulation /measurements and show excellent results for all types of real device effects like SCE, DIBL, mobility degradation, poly depletion, QME etc.read more
Citations
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Journal ArticleDOI
BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control
Sourabh Khandelwal,Yogesh Singh Chauhan,Darsen D. Lu,Sriramkumar Venugopalan,M. A. Karim,Angada B. Sachid,Bich-Yen Nguyen,O. Rozeau,O. Faynot,Ali M. Niknejad,C. Hu +10 more
TL;DR: In this article, the authors present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control.
Proceedings ArticleDOI
Impact of device geometry and doping concentration variation on electrical characteristics of 22nm FinFET
TL;DR: The results show that for Tfin of 3nm, t-ox of 1.5nm and fin height of 7nm has higher I-on-on and lower I-off-sub, while for Hof 7nm, the results show higher I–on–I–off and even lower I–off.
Proceedings ArticleDOI
Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region
TL;DR: In this article, the authors proposed a 6T subthreshold 1R-2W SRAM and 8T 2R 2R2W bit cell designs using 25nm FinFET transistors having independent READ and WRITE ports.
Proceedings ArticleDOI
Static and dynamic energy losses vs. temperature in different CMOS technologies
Piotr Kocanda,Andrzej Kos +1 more
TL;DR: Energy dissipation analysis in regards to supply voltage and temperature is presented, finding that static power dissipation, a result of existing leakage currents, rises with temperature.
Proceedings ArticleDOI
Nanoscale FinFET global parameter extraction for the BSIM-CMG model
TL;DR: Improvements are proposed on the BSIM-CMG extraction procedure to obtain a fitting over a wide range of Leff, which shows that a single set of model parameters is inadequate for a widerange of FinFET geometries.