Showing papers by "Tsunenobu Kimoto published in 2005"

Interface Properties of Metal–Oxide–Semiconductor Structures on 4H-SiC{0001} and (1120) Formed by N2O Oxidation

Abstract: 4H-SiC(0001), (0001), and (1120) have been directly oxidized by N2O at 1300°C, and metal–oxide–semiconductor (MOS) interfaces have been characterized. The interface state density has been significantly reduced by N2O oxidation on any face, compared to conventional wet O2 oxidation at 1150°C. Planar n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) fabricated on 4H-SiC(0001), (0001) and (1120) faces have shown effective channel mobilities of 26, 43, and 78 cm2/Vs, respectively. Secondary ion mass spectrometry analyses have revealed a clear pileup of nitrogen atoms near the MOS interface. The thickness of the interfacial transition layer can be decreased by N2O oxidation. The crystal face dependence of the interface structure is discussed. A simple consideration of chemistry indicates that NO, generated from the decomposition of N2O, may be a more efficient oxidant of carbon than O2.

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs

Abstract: In this paper, a fundamental investigation on short-channel effects (SCEs) in 4H-SiC MOSFETs is given. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (0001) and (1120) faces. In the fabricated MOSFETs, SCEs such as punchthrough behavior, decrease of threshold voltage, deterioration of subthreshold characteristics, and saturation of transconductance occur by reducing channel length. The critical channel lengths below which SCEs occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths obtained from the device simulation is in good agreement with the empirical relationship for Si MOSFETs. The critical channel lengths in the fabricated SiC MOSFETs are slightly longer than simulation results. The dependence of crystal face orientations on SCEs is hardly observed. Impacts of interface charge on the appearance of SCEs are discussed.

Carrier compensation near tail region in aluminum- or boron-implanted 4H-SiC(0001)

Abstract: Electrical behavior of implanted Al and B near implant-tail region in 4H–SiC (0001) after high-temperature annealing has been investigated. Depth profiles of Al and B acceptors determined by capacitance-voltage characteristics are compared with those of Al and B atoms measured by secondary-ion-mass spectrometry. For Al+ (aluminum-ion) implantation, slight in-diffusion of Al implants occurred in the initial stage of annealing at 1700°C. The profile of the Al-acceptor concentration in a “box-profile” region as well as an “implant-tail” region is in good agreement with that of the Al-atom concentration, indicating that nearly all of the implanted Al atoms, including the in-diffused Al atoms, work as Al acceptors. Several electrically deep centers were formed by Al+ implantation. For B+ (boron-ion) implantation, significant out- and in-diffusion of B implants occurred in the initial stage of annealing at 1700°C. A high density of B-related D centers exists near the tail region. In the tail region, the sum of B-acceptor concentration and D-center concentration corresponds to the B-atom concentration. C+ (carbon-ion) coimplantation with a ten times higher dose than B+ effectively suppressed the B diffusion, but additional deep centers were introduced by C+ coimplantation.

Switching characteristics of SiC JFET and Schottky diode in high-temperature dc-dc power converters

Abstract: This paper reports on SiC devices operating in a dc-dc buck converter under extremely high ambient temperatures. To this end, the authors packaged SiC JFET and Schottky diodes in thermally stable packages and built a high-temperature inductor. The converter was tested at ambient temperatures up to 400°C. Although the conduction loss of the SiC JFET increases slightly with increasing temperatures, the SiC JFET and Schottky diode continue normal operation because their switching characteristics show minimal change with temperature. This work further demonstrates the suitability of the SiC devices for high-temperature power converter applications.

Power Conversion with SiC Devices at Extremely High Ambient Temperatures

Abstract: This paper evaluates the capability of SiC devices for operation under extremely high ambient temperatures. To this end, the authors packaged SiC JFET and Schottky barrier diodes (SBD) in thermally stable packages and built a high-temperature inductor to be evaluated in a DC-DC buck converter. The DC characteristics of the SiC JFET devices were first measured at ambient temperatures ranging from room temperature up to 450 degC. The experimental results show that the device can operate at 450 degC, which is impossible for conventional Si devices, but as expected the current capability of the SiC JFET diminishes with rising temperatures. A DC-DC converter was then designed and built in accordance with the static characteristics of the SiC JFETs that were measured under extremely high ambient temperatures. The converter was tested up to an ambient temperature of 400 degC. The conduction loss of the SiC JFET increases slightly, as predicted from its DC characteristics, but its switching characteristics hardly change with increasing temperatures. Thus, SiC devices are well suited for operation in harsh temperature environments

4H-SiC epitaxial growth on SiC substrates with various off-angles

Abstract: Chemical vapor deposition of 4H-SiC on (0001) substrates with various off-angles from 1o to 45o has been investigated. On large-off-angled (15o-45o) substrates, very smooth surface morphology is obtained in the wide range of C/Si ratio. The micropipe dissociation during epitaxial growth is observed on 4o-45o off-angled substrates with a low C/Si ratio. The incorporation of nitrogen was dramatically suppressed by increasing C/Si ratio irrespective of substrate’s off-angle.

Technological Aspects of Ion Implantation in SiC Device Processes

Abstract: Technological aspects of ion implantation in SiC device processes are described. Annealing techniques to suppress surface roughening of implanted SiC (0001) are demonstrated. Trials to achieve a low sheet resistance are described for n-type and p-type doping. Implantation into the (11-20) face is also presented. Electrical behaviors of implants near implanted tail regions are discussed based on experiments.

Short-Channel Effects in 4H-SiC MOSFETs

Abstract: Short-channel effects in SiC MOSFETs have been investigated. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (000-1) and (11-20) faces.^Short-channel effects such as punchthrough behavior, decrease of threshold voltage and deterioration of subthreshold characteristics are observed. Furthermore, the critical channel lengths below which short-channel effects occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths in the fabricated SiC MOSFETs are in agreement with those obtained from the device simulation. The results are also in agreement with the empirical relationship for Si MOSFETs.

Reduction of stacking faults in fast epitaxial growth of 4H-SiC and its impacts on high-voltage Schottky diodes

Abstract: Generation of stacking faults (SFs) in fast epitaxial growth of 4H-SiC(0001) has been reduced in vertical hot-wall chemical vapor deposition (CVD). 52 µm-thick epilayers with and without SFs are used to investigate impacts of SFs on the performance of Schottky barrier diodes (SBDs). The density, shape and structure of stacking faults have been characterized by cathodeluminescence (CL), photoluminescence (PL) and high-resolution transmission electron microscopy (HR-TEM). These analyses indicate that most (> 75 %) SFs with an 8H structure are generated near the epilayer/substrate interface during CVD. It is also revealed that the SFs cause the lowering of Schottky barrier height as well as the decrease of breakdown voltage.

Fast epitaxial growth of high-purity 4H-SiC(\(000\bar 1\)) in a vertical hot-wall chemical vapor deposition) in a vertical hot-wall chemical vapor deposition

Abstract: 4H-SiC(\(000\bar 1\)) epitaxial layers with a 14–28-µm thickness have been grown at high growth rates of 14–19 µm/h by chimney-type, vertical hot-wall, chemical vapor deposition (CVD) at 1,750°C. The 3C hillocks are formed on the epilayers grown under relatively low C/Si ratios. When grown at a relatively higher C/Si ratio of 0.6, the hillock density has been decreased to 1 cm−2. Under the C-rich condition, the concentrations of residual impurity (nitrogen) and intrinsic defects (Z1/2 and EH6/7) have been reduced. When growth has been performed at low C/Si ratios of 0.4 and 0.5, all the micropipes in the substrates (more than 100 micropipes for each condition) have been closed during CVD growth.

Improved Surface Morphology and Background Doping Concentration in 4H-SiC(000-1) Epitaxial Growth by Hot-Wall CVD

Abstract: 4H-SiC layers have been homoepitaxially grown on off-axis 4H-SiC(000-1) under various conditions by horizontal hot-wall CVD. Improvement of surface morphology and reduction of background doping concentration have been achieved. Surface morphology grown on the (000-1) C face strongly depends on the C/Si ratio at 1500 °C, and hillock-like surface defects can be eliminate by increasing growth temperature to 1600 °C. Site-competition behavior is clearly observed under low-pressure growth conditions even on the (000-1) C face. The lowest doping concentration has been determined to be 6.0x1014 cm-3. A trial of high-speed growth on the (000-1) C face and deep level analysis are also discussed.

Electrical Behavior of Implanted Aluminum and Boron near Tail Region in 4H-SiC after High-Temperature Annealing

Abstract: The authors have investigated electrical behavior of implanted Al and B atoms near a “tail” region in 4H-SiC (0001) after high-temperature annealing. For aluminum-ion (Al+) implantation, slight in-diffusion of Al implants occurs in the initial stage of annealing at 1700 °C. Nearly all of implanted Al atoms, including the in-diffused Al atoms were activated by annealing at 1700 °C for 1 min. Several electrically deep centers are formed by Al+ implantation. The concentrations of the centers are 3-4 orders-of-magnitude lower than that of implanted Al-atom concentration. For boron-ion (B+) implantation, significant out- and in-diffusion of B implants occur in the initial stage of annealing at 1700 °C. Most of the in-diffused B implants work as B acceptors. A high density of B-related D center exists near the tail region. To suppress the B diffusion, a ten-times higher dose of carbon-ion (C+) co-implantation is effective. However, high concentrations of additional deep centers are introduced by such high-dose C+ co-implantation.

Optical-capacitance-transient spectroscopy study for deep levels in 4H-SiC epilayer grown by cold wall chemical vapor deposition

Abstract: Optical cross sections for deep levels in 4H-SiC grown by cold wall chemical vapor deposition (CVD) were investigated by optical-capacitance-transient spectroscopy (O-CTS). By fitting the measured data with the theoretically calculated curve, we obtained optical excitation energy of 1.50 eV for the Z1/2 center. We also obtained its thermal activation energy of 0.61 eV. From these energy values and previously reported the capture barrier and the negative-U property, we drew the configuration coordinate diagram of the Z1/2 center, and then the Frank-Condon shift of 0.96-0.97 eV was estimated. In addition, the EH6/7 center was also characterized by O-CTS measurements. Introduction Crystalline quality of silicon carbide (SiC) has been improved in past decades and thus unipolar devices have already been commercialized. However, the minority carrier lifetime, which affects bipolar device operation, is very short even in high quality SiC crystals. Therefore deep levels, which influence recombination of minority carriers, should be characterized in order to know carrier dynamics in SiC. Usually, the deep level transient spectroscopy (DLTS) is employed for this purpose. The DLTS reveals the activation energy of carriers from deep levels. The optical excitation energy is another important parameter for drawing the configuration coordinate diagrams which graphically shows carrier dynamics at deep levels. In this study we have characterized deep levels in a 4H-SiC epilayer grown by cold wall chemical vapor deposition (CVD) using the optical-capacitance-transient spectroscopy (O-CTS), which observes capacitance transient due to optically excited carriers from deep levels within the depletion region [1]. By performing O-CTS, we obtained optical excitation energies for deep levels in 4H-SiC. Experiments The sample used in this work was an n-type 4H-SiC epilayer grown by horizontal cold wall CVD on a 4H-SiC (0001) Si face substrate with 8° inclination toward <1120>. The source gases for CVD were silane and propane, and the growth temperature was 1500°C. The source gas ratio (the C/Si ratio) was 1.5. Au was thermally evaporated on the epitaxial layer to form Schottky contacts. The Au contacts were thin enough to be transparent for excitation light, and the contact area was of 1.77 mm. By using the Au contacts, capacitance-voltage (C-V), deep level transient spectroscopy (DLTS) and O-CTS measurements were performed. In the O-CTS measurements, we detected a capacitance transient signal caused by the optical excitation of carriers from deep levels and the signal was converted to an O-CTS spectrum by the rate window scan method. For the excitation light, a 300 W Xe lamp was employed and the light was passed through a monochromater and focused onto the Schottky contact region. The photon flux and the photon energy range of the excitation light are of the order of 10 cms and 1.02-2.38 eV, respectively. Materials Science Forum Online: 2005-05-15 ISSN: 1662-9752, Vols. 483-485, pp 381-384 doi:10.4028/www.scientific.net/MSF.483-485.381 © 2005 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-11/03/20,12:19:45) Results and Discussions From the C-V measurements, the sample has the net donor concentration of 3.0×10 cm. The DLTS spectrum for this sample with a time constant of 76 ms is shown in Fig. 1. Three peaks are observed in this spectrum at around 290 K, 380 K and 600 K and we name them peak A, B and C. From the Arrhenius plot, the peak A shows an activation energy of 0.61 eV and a capture cross section of 1.2×10 cm, and these values are similar to the reported values for the Z1/2 center [2,3]. Thus, the peak A can be identified as the Z1/2 center and its concentration is estimated to be 3.0×10 cm from the peak height. Figure 2 shows O-CTS spectra with the photon energy range of 1.02-1.82 eV at 180 K where the Z1/2 center is not thermally excited. Without illumination, no peak was observed within the measurement time constant. With 1.02 eV illumination, a peak was observed around 300 s while, with 1.77 and 1.82 eV illumination, time constant of the peak became around 10 s and 3 s, respectively. From similarity in height between the O-CTS peak and the Z1/2 center peak in the DLTS spectrum (∼5fF), we believe that this O-CTS peak is caused by the Z1/2 center. From the time constants and the photon flux, we obtained the optical cross section, σ, for the Z1/2 center as shown in Fig. 3. The data are fitted by a theoretical model proposed by Chantre et al. [4], , * 2 , , 4 , ) ( exp ) / 1 ( ) 1 ( 1

Selective Embedded Growth of 4H–SiC Trenches in 4H–SiC(0001) Substrates Using Carbon Mask

Abstract: Selective embedded growth of 4H–SiC trenches in SiC(0001) substrates utilizing a carbon mask by chemical vapor deposition has been investigated. The SiC trenches have been successfully embedded, and the carbon mask is successfully removed by thermal oxidation. The growth rate inside the SiC trench region on the masked SiC substrates is three times higher than that on nonmasked planar SiC substrates. Micro-Raman scattering measurements reveal that the embedded region is homoepitaxial 4H–SiC.

Growth of Nonpolar AlN and AlGaN on 4H-SiC (1-100) by Molecular Beam Epitaxy

Abstract: AlN and AlGaN have been grown on 4H-SiC (1-100) substrates by rf-plasma molecular beam epitaxy. AlN assumes a metastable 4H structure to match the in-plane stacking arrangement of the substrate. Initial 2D nucleation of 4H-AlN is revealed by reflection high-energy electron diffraction. The epitaxial quality is evidenced by narrow x-ray diffraction ω-scan line widths less than 100 arcsec for symmetric and asymmetric reflections. Structural characterization results for AlGaN/AlN multiple quantum wells are also presented.

Midgap Levels in As-Grown 4H-SiC Epilayers Investigated by DLTS

Abstract: Midgap levels in 4H-SiC epilayers have been investigated by DLTS. The EH6/7 center (Ec-1.55 eV) is the dominant deep level as observed in DLTS spectra from n-type epilayers. The activation energy of EH6/7 center is unchanged regardless of applied electric fields, indicating that the charge state of EH6/7 center may be neutral after electron emission (acceptor-like). A DLTS spectrum for a p-type epilayer in the temperature range from 90 to 830 K is dominated by two peaks, D center and a deep trap at 1.49 eV from the valence band edge. Minority carrier traps have been also investigated by DLTS using pn diodes. Two minority carrier traps with activation energies of 1.0 eV and 1.43 eV have been detected.

Dose designing for high-voltage 4H-SiC RESURF MOSFETs - device simulation and fabrication

Abstract: Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.