Showing papers by "Tsunenobu Kimoto published in 2016"

Growth of Shockley type stacking faults upon forward degradation in 4H-SiC p-i-n diodes

Abstract: The growth of Shockley type stacking faults in p-i-n diodes fabricated on the C-face of 4H-SiC during forward current operation was investigated using Berg-Barrett X-ray topography and photoluminescence imaging. After forward current experiment, Shockley type stacking faults were generated from very short portions of basal plane dislocations lower than the conversion points to threading edge dislocations in the epitaxial layer. The growth behavior of Shockley type stacking faults was discussed. Growth of stacking faults in the substrates was not observed.

Promise and Challenges of High-Voltage SiC Bipolar Power Devices

Abstract: Although various silicon carbide (SiC) power devices with very high blocking voltages over 10 kV have been demonstrated, basic issues associated with the device operation are still not well understood. In this paper, the promise and limitations of high-voltage SiC bipolar devices are presented, taking account of the injection-level dependence of carrier lifetimes. It is shown that the major limitation of SiC bipolar devices originates from band-to-band recombination, which becomes significant at a high-injection level. A trial of unipolar/bipolar hybrid operation to reduce power loss is introduced, and an 11 kV SiC hybrid (merged pin-Schottky) diodes is experimentally demonstrated. The fabricated diodes with an epitaxial anode exhibit much better forward characteristics than diodes with an implanted anode. The temperature dependence of forward characteristics is discussed.

Control of carrier lifetime of thick n-type 4H-SiC epilayers by high-temperature Ar annealing

Abstract: We investigated the carrier lifetime and Z1/2 center density of thick n-type 4H-SiC epilayers, which were oxidized and subsequently annealed in Ar at high temperatures. The Z1/2 center density decreased below the detection limit in the region to, at least, a 130 µm depth by thermal oxidation. After subsequent high-temperature annealing, the Z1/2 center density increased with increasing annealing temperature, while the distribution of the Z1/2 center density was nearly uniform to a 130 µm depth. The carrier lifetime could be controlled from 26 to 2.4 µs by changing the annealing temperature from 1600 to 1800 °C.

Interface state density of SiO2/p-type 4H-SiC (0001), (112¯0), (11¯00) metal-oxide-semiconductor structures characterized by low-temperature subthreshold slopes

Abstract: Interface properties of heavily Al-doped 4H-SiC ( 0001) (Si-face), ( 112¯0) (a-face), and ( 11¯00) (m-face) metal-oxide-semiconductor (MOS) structures were characterized from the low-temperature gate characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). From low-temperature subthreshold slopes, interface state density (Dit) at very shallow energy levels (ET) near the conduction band edge (Ec) was evaluated. We discovered that the Dit near Ec (Ec − 0.01 eV < ET < Ec) increases in MOS structures with higher Al doping density for every crystal face (Si-, a-, and m-face). Linear correlation is observed between the channel mobility and Dit near Ec, and we concluded that the mobility drop observed in heavily doped MOSFETs is mainly caused by the increase of Dit near Ec.

Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices

Abstract: We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

Hall scattering factors in p-type 4H-SiC with various doping concentrations

Abstract: The Hall scattering factor (γH) in p-type 4H-SiC with various aluminum doping concentrations of 5.8 × 1014–7.1 × 1018 cm−3 was investigated from 300 to 900 K. γH was determined by comparing the Hall coefficient with the theoretical carrier concentration derived from acceptor and donor concentrations obtained from secondary ion mass spectrometry and capacitance–voltage measurements. γH decreased with increasing temperature or doping concentration; γH = 1–0.4 for the doping concentration of 5.8 × 1014 cm−3 and γH = 0.5–0.2 for the doping concentration of 7.1 × 1018 cm−3. The dependence might be caused by the anisotropic and nonparabolic valence band structure of 4H-SiC.

Demonstration of 3 kV 4H-SiC reverse blocking MOSFET

Abstract: The authors developed 3 kV 4H-SIC reverse blocking (RB) metal-oxide-semiconductor field-effect transistors (MOSFETs) for the first time. To achieve reverse blocking capability, the n+-substrate layer was removed by polishing, and both a Schottky contact and edge-termination structure were introduced onto the wafer backside. Fabricated SiC RB MOSFETs exhibited good Schottky characteristics, and measured differential specific on-resistance was 20 mΩ·cm2. Both forward and reverse blocking voltages of RB MOSFETs are higher than 3 kV. On-state power loss of a developed RB MOSFET is 35% lower than that of anti-serially connected standard 3 kV SiC MOSFETs, demonstrating the advantage of the developed RB MOSFET as a high-voltage bi-directional switch.

Stress Characterization of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) using Raman Spectroscopy and the Finite Element Method.

Abstract: We measured the depolarized and polarized Raman spectra of a 4H-SiC metal-oxide–semiconductor field-effect transistor (MOSFET) and found that compressive stress of approximately 20 MPa occurs under the source and gate electrodes and tensile stress of approximately 10 MPa occurs between the source and gate electrodes. The experimental result was in close agreement with the result obtained by calculation using the finite element method (FEM). A combination of Raman spectroscopy and FEM provides much data on the stresses in 4H-SiC MOSFET.

Surface passivation on 4H-SiC epitaxial layers by SiO2 with POCl3 annealing

Abstract: We investigated surface passivation on 4H-SiC epitaxial layers with deposited or thermally grown SiO2 followed by POCl3 annealing. The measured carrier lifetime in a p-type epilayer with deposited SiO2 was limited to 0.5 µs and it was improved to 3.0 µs after POCl3 annealing. In an n-type epilayer, a measured carrier lifetime of 5.8 µs was improved to 12 µs after POCl3 annealing. We found a clear relationship between the measured carrier lifetime and the interface state density at SiO2/n-SiC after POCl3 annealing, suggesting that the reduction in interface state density lowered the surface recombination velocity on the 4H-SiC.

Effect of NiO crystallinity on forming characteristics in Pt/NiO/Pt cells as resistive switching memories

Abstract: Resistive switching (RS) in metal/oxide/metal stack structures plays a key role in resistive RAM. The formation and rupture of conductive filaments have been widely accepted as an origin of RS mechanism especially in binary transition metal oxides. Forming exhibits some analogies with a dielectric breakdown of SiO2 thin films. In this study, Time-Dependent Forming (TDF) characteristics of Pt/NiO/Pt stack structures have been investigated. The results revealed that the formation of conductive filaments at the forming process by applying constant voltage followed a weakest-link theory and that the weakest spots were almost randomly distributed in NiO thin films according to the Poisson statistics. Furthermore, the distribution of TDF characteristics depends on NiO crystallinity. A small variation of initial resistance tends to result in a large variation of time to forming and vice versa.

Ion implantation technology in SiC for high-voltage/high-temperature devices

Abstract: Electrical activation of implanted dopants and defect generation in SiC have been investigated. A nearly perfect (> 95%) electrical activation can be obtained including the implant tail region after annealing at 1650–1700 °C. The majority of point defects generated in implanted SiC can remarkably be reduced by thermal oxidation. The high activation ratio of implanted Al acceptors is a key factor for fabricating effective junction termination structures in high-voltage SiC devices. Recent high-quality semi-insulating SiC wafers offer the opportunity of high-temperature SiC integrated devices, which can be fabricated by only ion implantation without an epitaxial growth process.

Suppression of the forward degradation in 4H-SiC PiN diodes by employing a recombination-enhanced buffer layer

Abstract: Application of highly N-doped buffer layers or a (N+B)-doped buffer layer to PiN diodes to suppress the expansion of Shockley stacking faults (SSFs) from the epilayer/substrate interface was studied. These buffer layers showed very short minority carrier lifetimes of 30–200 ns at 250°C. The PiN diodes were fabricated with buffer layers of various thicknesses and were then tested under high current injection conditions of 600A/cm2. The thicker buffer layers with shorter minority carrier lifetimes demonstrated the suppression of SSFs expansion and thus that of diode degradation.

Correlation between shapes of Shockley stacking faults and structure of basal plane dislocations in 4H-SiC epilayers

Abstract: Abstract Shockley-type stacking faults expanded in 4H–SiC epilayers induced by ultraviolet illumination were investigated using a photoluminescence imaging method, a photoluminescence mapping method and X-ray topography. After ultraviolet illumination, more than 30 patterns of Shockley-type stacking faults which expanded from perfect basal plane dislocations were observed by photoluminescence imaging. The initial basal plane dislocations were crystallographically classified, and individual shapes of expanded Shockley-type stacking faults were predicted. The correspondence between the predicted shapes and observed ones was discussed.

Strong impact of the initial III/V ratio on the crystalline quality of an AlN layer grown by rf-plasma-assisted molecular-beam epitaxy

Abstract: The initial Al/N ratio for AlN growth of plasma-assisted molecular-beam epitaxy without plasma stabilization is investigated. The in situ growth rate of AlN gradually increased and its temporal variation corresponded to that of nitrogen atoms, which indicated that the initial Al/N ratio was excessively Al-rich. For AlN growth, such a high-Al/N-ratio condition resulted in a three-dimensional growth mode in the initial stage of the growth, and AlN with high threading dislocation density was obtained. By controlling the initial Al/N ratio by introducing a short standby time, the resulting two-dimensional initial growth mode leads to high-quality growth of AlN.

Modeling of surface roughness scattering in nanowires based on atomistic wave function: Application to hole mobility in rectangular germanium nanowires

Abstract: The authors present a calculation model of surface roughness scattering (SRS) in nanowires (NWs) based on atomistic description of electronic states by an $s{p}^{3}{d}^{5}{s}^{*}$ tight-binding scheme, and then this model is applied to hole transport in rectangular cross-sectional germanium (Ge) NWs. In this SRS model, the change of electronic band structures due to width or height reduction is first computed, and then it is expressed using an equivalent potential near the surface. The perturbation corresponding to a surface roughness is calculated from this equivalent potential. Using the aforementioned SRS model, hole mobility in Ge NWs was computed taking into account phonon scattering and SRS. The impacts of SRS on hole mobility in Ge NWs were analyzed, focusing on the valence band structure and hole states of NWs. The main results are as follows. At low hole density, the impacts of SRS are strongly dependent on NW geometry, and Ge NWs with high phonon-limited hole mobility, such as rectangular cross-sectional [110]-oriented NWs with large height along the [001] direction and square cross-sectional [111]-oriented NWs, tend to be less affected by SRS. At high hole density, however, the geometry dependence of hole mobility becomes weaker. These are understood from the nature of hole states and the valence band structure.

Strain control in AlN top layer by inserting an ultrathin GaN interlayer on an AlN template coherently grown on SiC(0001) by PAMBE

Abstract: authoren We propose partially relaxed ultrathin GaN interlayer for strain control of AlN on SiC substrates. According to the degree of relaxation of the GaN interlayer, the lattice constant of the interlayer changes from that of SiC to that of bulk GaN, which leads to strain control of an AlN top layer grown on the interlayer. Growth of these layers is conducted by plasma-assisted molecular beam epitaxy. Before growing the interlayer, an AlN layer coherently grown on SiC is used as a template layer. The interlayers that have different degrees of relaxation are successfully obtained by changing the interlayer thickness. As a result, strain values of the AlN top layer grown on the interlayers are widely controlled from compressive (−0.53%) to tensile (+ 0.07%). TEM observation revealed the relaxation is induced by U-shaped half-loop dislocations originating from the GaN interlayer.

Analysis of ballistic and quasi-ballistic hole transport properties in germanium nanowires based on an extended “Top of the Barrier” model

Abstract: The ballistic hole transport properties in rectangular cross-sectional germanium nanowire transistors with various geometries were studied based on the “Top of the Barrier” model. Then, by an extension of this model, the quasi-ballistic hole transport was discussed taking into account phonon and surface roughness scattering in the channel and source-to-drain direct tunneling. Among several nanowire geometries targeted in this study, the [1 1 0]-oriented nanowire with large height along [1 1 ¯ 0] ([1 1 0]/(1 1 ¯ 0) NW) exhibited the largest ballistic current. This was understood from its large density of states and resulting high hole density. Large density of states, however, enhances backscattering in the channel. An approximation analysis of quasi-ballistic transport suggested that the [1 1 0]/(0 0 1) NW with higher mobility can outperform [1 1 0]/(1 1 ¯ 0) NW when scattering and tunneling are considered.

Solubility and diffusion of chromium in 4H-SiC

Abstract: The solubility and diffusivity of Cr atoms in 4H-SiC epilayers are investigated. The formation energy of 4H-SiC containing Cr has been calculated by first-principles calculation. Si sites have been found to be more stable than C sites or interstitial sites for Cr atoms owing to the lower formation energy. The solubility estimated from the formation energy coincides with the saturated Cr concentration in SiC crystals grown by solution growth. The diffusivity of implanted Cr atoms (located at interstitial sites) was not affected by the charge states of Cr atoms and/or vacancies such as carbon vacancies and silicon vacancies, implying the interstitial diffusion of Cr atoms.

ESR Study on Hydrogen Passivation of Intrinsic Defects in p-Type and Semi-Insulating 4H-SiC

Abstract: We studied the hydrogen passivation/depassivation of four types of intrinsic defects (EI5/6, HEI7/8, HEI9/10, and P6/7) in p-type and semi-insulating 4H-SiC by means of electron spin resonance (ESR) for examining the origin of career-lifetime-killing defects. We suggest that the HEI7/8 and P6/7 centers are the strongest candidate for the origin of the lifetime-killing defects.

Suppression of the forward degradation in 4H-SiC PiN diodes by employing a recombination-enhanced buffer layer

Abstract: Application of highly N-doped buffer layers or a (N+B)-doped buffer layer to PiN diodes to suppress the expansion of Shockley stacking faults (SSFs) from the epilayer/substrate interface was studied. These buffer layers showed very short minority carrier lifetimes of 30–200 ns at 250°C. The PiN diodes were fabricated with buffer layers of various thicknesses and were then tested under high current injection conditions of 600A/cm2. The thicker buffer layers with shorter minority carrier lifetimes demonstrated the suppression of SSFs expansion and thus that of diode degradation.

Impact of annealing temperature on surface passivation of SiC epitaxial layers with deposited SiO 2 followed by POCl 3 annealing

Abstract: We investigate an impact of annealing temperature on surface passivation of SiC epitaxial layers with deposited SiO 2 followed by POCl 3 annealing. The POCl 3 annealing process consists of two steps: (i) thermal annealing in POCl 3 and (ii) subsequent thermal annealing in pure N 2 . We find that the annealing temperature of the subsequent N 2 annealing is important to reduce surface recombination on SiC. For surface passivation, N 2 annealing at high temperature at 1000° C is necessary.

Theoretical analysis of high-field hole transport in germanium and silicon nanowires

Abstract: High-field hole transport in Ge nanowires was studied using Boltzmann's transport equation. The behavior of drift velocity was analyzed based on the highly non-parabolic valence band structure. High-field hole transport properties in Si nanowires were also calculated, and the differences between Ge and Si nanowires were discussed.