U
Uddalak Bhattacharya
Researcher at Intel
Publications - 72
Citations - 3349
Uddalak Bhattacharya is an academic researcher from Intel. The author has contributed to research in topics: Static random-access memory & CMOS. The author has an hindex of 26, co-authored 70 publications receiving 3235 citations. Previous affiliations of Uddalak Bhattacharya include University of California, Santa Barbara.
Papers
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Journal ArticleDOI
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation
Hyunwoo Nho,Pramod Kolar,Fatih Hamzaoglu,Yih Wang,Eric Karl,Yong-Gee Ng,Uddalak Bhattacharya,Kevin Zhang +7 more
TL;DR: An adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die is introduced.
Proceedings ArticleDOI
SRAM design on 65nm CMOS technology with integrated leakage reduction scheme
Kevin Zhang,Uddalak Bhattacharya,Zhanping Chen,Fatih Hamzaoglu,D. Murray,N. Vallepalli,Yih Wang,B. Zheng,Mark T. Bohr +8 more
TL;DR: In this article, a 4Mb SRAM is designed and fabricated on a 65nm CMOS technology, which features a 0.57 /spl mu/m/sup 2/6T cell with large noise margin down to 0.7V for low-voltage operation.
Proceedings Article
A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
Yih Wang,Hong Jo Ahn,Uddalak Bhattacharya,Zhanping Chen,T. Coan,Fatih Hamzaoglu,Hafez Walid M,Chia-Hong Jan,Pramod Kolar,Sarvesh H. Kulkarni,J. Lin,Yong-Gee Ng,Ian R. Post,Liqiong Wei,Ying Zhang,Kevin Zhang,Mark T. Bohr +16 more
TL;DR: A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications that improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage.
Journal ArticleDOI
SCALING OF InGaAs/InAlAsHBTs FOR HIGH SPEED MIXED-SIGNAL AND mm-WAVE ICs
Mark J. W. Rodwell,Miguel Urteaga,Y. Betser,T. Mathew,P. Krishnan,Dennis W. Scott,S. Jaganathan,D. Mensa,J. Guthrie,Rajasekhar Pullela,Q. Lee,B. Agarwal,Uddalak Bhattacharya,Stephen I. Long,S.C. Martin,R.P. Smith +15 more
TL;DR: In this article, the authors show that high bandwidths are obtained with heterojunction bipolar transistors by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction width.
Journal ArticleDOI
DC - 725 GHz sampling circuits and subpicosecond nonlinear transmission lines using elevated coplanar waveguide
TL;DR: In this paper, nonlinear transmission lines (NLTL's) fabricated with Schottky diodes on GaAs were used to electrically generate 3.7-V step functions that had a measured 10%-90% fall time of 0.68 ps.