Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Machine-Learning tasks are becoming pervasive in a broad range of domains, and in a broad range of systems (from embedded systems to data centers). At the same time, a small set of machine-learning algorithms (especially Convolutional and Deep Neural Networks, i.e., CNNs and DNNs) are proving to be state-of-the-art across many applications. As architectures evolve towards heterogeneous multi-cores composed of a mix of cores and accelerators, a machine-learning accelerator can achieve the rare combination of efficiency (due to the small number of target algorithms) and broad application scope. Until now, most machine-learning accelerator designs have focused on efficiently implementing the computational part of the algorithms. However, recent state-of-the-art CNNs and DNNs are characterized by their large size. In this study, we design an accelerator for large-scale CNNs and DNNs, with a special emphasis on the impact of memory on accelerator design, performance and energy. We show that it is possible to design an accelerator with a high throughput, capable of performing 452 GOP/s (key NN operations such as synaptic weight multiplications and neurons outputs additions) in a small footprint of 3.02 mm2 and 485 mW; compared to a 128-bit 2GHz SIMD processor, the accelerator is 117.87x faster, and it can reduce the total energy by 21.08x. The accelerator characteristics are obtained after layout at 65 nm. Such a high throughput in a small footprint can open up the usage of state-of-the-art machine-learning algorithms in a broad set of systems and for a broad set of applications.

https://novel.ict.ac.cn/ychen/pdf/DianNao.pdf

DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning

http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor perfor- mance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire mod- els (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model Non-uniform Cache Access (NUCA). We not only adopt state-of-the-art design space exploration strategies for NUCA, we also enhance this exploration by considering on-chip network contention and a wider spectrum of wiring and routing choices. We present a validation analysis of the new tool (to be released as CACTI 6.0) and present a case study to showcase how the tool can improve architecture research methodologies. Keywords: cache models, non-uniform cache archi- tectures (NUCA), memory hierarchies, on-chip intercon- nects.

/pdf/optimizing-nuca-organizations-and-wiring-alternatives-for-3rrqqn2dbv.pdf

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

A new type of device, the band-to-band tunnel transistor, which has atomically thin molybdenum disulfide as the active channel, operates in a fundamentally different way from a conventional silicon (MOSFET) transistor; it has turn-on characteristics and low-power operation that are better than those of state-of-the-art MOSFETs or any tunnelling transistor reported so far. Traditional transistor technology is fast approaching its fundamental limits, and two-dimensional semiconducting materials such as molybdenum disulfide (MoS2) are seen as possible replacements for silicon in a next generation of high-density, lower-power chip electronics. A particularly promising prospect is their potential in band-to-band tunnel transistors, which operate in a fundamentally different way from conventional silicon (MOSFET) transistors. So far, few such devices with overall characteristics better than silicon transistors have been demonstrated. Now Kaustav Banerjee et al. have built a tunnel transistor by making a vertical structure with atomically thin MoS2 as the active channel and germanium as the source electrode. It has turn-on characteristics and low-power operation that are better than those of existing silicon transistors, and the results will be of interest in a range of electronic applications including low-power integrated circuits, as well as ultra-sensitive bio sensors or gas sensors. The fast growth of information technology has been sustained by continuous scaling down of the silicon-based metal–oxide field-effect transistor. However, such technology faces two major challenges to further scaling. First, the device electrostatics (the ability of the transistor’s gate electrode to control its channel potential) are degraded when the channel length is decreased, using conventional bulk materials such as silicon as the channel. Recently, two-dimensional semiconducting materials1,2,3,4,5,6,7 have emerged as promising candidates to replace silicon, as they can maintain excellent device electrostatics even at much reduced channel lengths. The second, more severe, challenge is that the supply voltage can no longer be scaled down by the same factor as the transistor dimensions because of the fundamental thermionic limitation of the steepness of turn-on characteristics, or subthreshold swing8,9. To enable scaling to continue without a power penalty, a different transistor mechanism is required to obtain subthermionic subthreshold swing, such as band-to-band tunnelling10,11,12,13,14,15,16. Here we demonstrate band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on; subthreshold swing is a minimum of 3.9 millivolts per decade and an average of 31.1 millivolts per decade for four decades of drain current at room temperature. By using highly doped germanium as the source and atomically thin molybdenum disulfide as the channel, a vertical heterostructure is built with excellent electrostatics, a strain-free heterointerface, a low tunnelling barrier, and a large tunnelling area. Our atomically thin and layered semiconducting-channel tunnel-FET (ATLAS-TFET) is the only planar architecture tunnel-FET to achieve subthermionic subthreshold swing over four decades of drain current, as recommended in ref. 17, and is also the only tunnel-FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts. Our device is at present the thinnest-channel subthermionic transistor, and has the potential to open up new avenues for ultra-dense and low-power integrated circuits, as well as for ultra-sensitive biosensors and gas sensors18,19,20,21.

A subthermionic tunnel field-effect transistor with an atomically thin channel.

Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications It also plays an important role in power-gating to cut off leakage power for higher energy efficiency However, existing on-chip state backup solutions for D flip–flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip–flops designs using negative capacitance FET These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, eg, 24 fJ in energy and 11 ns in time for one proposed nonvolatile DFF with a supply power of 080 V

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops

We present an analysis of electrical noise in III-V heterojunction TFET (HTFET) Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction HTFET exhibits 40% less relative RTN amplitude at 03 V at gate lengths around 20 nm, over subthreshold Si-FinFET RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET In the range 10 GHz or more with operating voltages exceeding 03 V, HTFET input noise is worse due to the dominance of shot noise A differential amplifier with active load is used to examine the electrical noise performance at circuit level We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance

Electrical Noise in Heterojunction Interband Tunnel FETs

Video analytics introduce new levels of intelligence to automated scene understanding. Neuromorphic algorithms, such as HMAX, are proposed as robust and accurate algorithms that mimic the processing in the visual cortex of the brain. HMAX, for instance, is a versatile algorithm that can be repurposed to target several visual recognition applications. This paper presents the design and evaluation of hardware accelerators for extracting visual features for universal recognition. The recognition applications include object recognition, face identification, facial expression recognition, and action recognition. These accelerators were validated on a multi-FPGA platform and significant performance enhancement and power efficiencies were demonstrated when compared to CMP and GPU platforms. Results demonstrate as much as 7.6X speedup and 12.8X more power-efficient performance when compared to those platforms.

/pdf/accelerating-neuromorphic-vision-algorithms-for-recognition-4ectgf6mhq.pdf

Accelerating neuromorphic vision algorithms for recognition

Radiation-induced single-event upset (SEU) has become a key challenge for cloud computing. The proposed introduction of low bandgap materials (Ge, III-Vs) as channel replacement and steep switching devices for low-voltage applications may induce radiation reliability issues due to their low ionization energy and device architecture. In this paper, the soft-error generation and propagation in Si FinFET, III-V FinFET, and III-V Hetero-junction tunnel FET (HTFET) are investigated using device and circuit simulation. III-V FinFET shows enhanced charge collection compared with Si FinFET, whereas HTFET shows significant reduction of the bipolar gain effect and charge collection. Soft-error rate (SER) evaluation methodology has been proposed for these emerging devices based on the critical LET extraction. SRAM bit flip, electrical masking effect, and latching window masking effect have been analyzed with supply voltage scaling. The SER evaluation of SRAM and logic shows that HTFET-based circuits are promising for radiation resilient ultra-low power applications. III-V FinFET shows increased SER for SRAM for ${\rm V}_{\rm DD}$ range of 0.3–0.8 Vand reduced logic SER below 0.5 V compared with Si FinFET.

/pdf/soft-error-performance-evaluation-on-emerging-low-power-3txnqtg9ny.pdf

Soft-Error Performance Evaluation on Emerging Low Power Devices

Although the superior subthreshold characteristics of steep-slope devices can help power up more cores, researchers still need CMOS technology to accelerate sequential applications, because it can reach higher frequencies. Device-level heterogeneous multicores can give the best of both worlds, but they need smart resource management to realize this promise. In this article, the authors discuss device-level heterogeneous multicores and various resource-management schemes for reaching higher energy efficiency.

Vijaykrishnan Narayanan

Papers

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops

Electrical Noise in Heterojunction Interband Tunnel FETs

Accelerating neuromorphic vision algorithms for recognition

Soft-Error Performance Evaluation on Emerging Low Power Devices

Steep-Slope Devices: From Dark to Dim Silicon