Showing papers by "Cadence Design Systems published in 2016"

USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA

Abstract: Quantum-dot cellular automata (QCA) is an emerging technology, conceived in face of nanoscale limitations of CMOS circuits, with exceptional integration density, impressive switching frequency, and remarkable low-power characteristics. Several of the current challenges toward the progress of QCA technology is related to the automation of the design process and integration into existing design flows. In this regard, this paper proposes the universal, scalable, efficient (USE), and easily manufacturable clocking scheme. It solves one of the most limiting factors of existing clock schemes, the implementation of feedback paths and easy routing of QCA-based circuits. Consequently, USE facilitates considerably the development of standard cell libraries and design tools for this technology, besides avoiding thermodynamics problems. Case studies presented in this paper reveal an area reduction of up to factor 5 and delay decrease by up to factor 3 in comparison with an existing advanced clocking scheme.

Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication

Abstract: A polar transmitter (TX) is implemented at 60 GHz, enabling a power amplifier (PA) to operate in saturation where efficiency is highest, even when handling higher order modulations such as QPSK and 16-QAM. The phase path is upconverted by I-Q mixers, while the amplitude path modulates an RF-DAC. Aimed at 802.11ad applications, the 10 GS/s (i.e., 6x-oversampled) polar TX realizes more than 30 dB alias attenuation, and the input bandwidth exceeds 3.1 GHz. The PA saturated output power is 10.8 dBm with 29.8% drain efficiency at the maximum RF-DAC code. Average output power is 8.1 dBm with 22.3% drain efficiency at $-20.7\;\text{dB}$ EVM for QPSK modulation without RF-DAC predistortion. The corresponding 16-QAM values are: 7.2 dBm average output power with 19.8% efficiency at $-16.5\;\text{dB}$ EVM. With predistortion, a QPSK modulated output achieves 5.3 dBm average power with 15.3% efficiency at $-23.6\;\text{dB}$ EVM, while 3.6 dBm average power with 11.6% efficiency at $-18.1\;\text{dB}$ EVM is realized for 16-QAM. For a sampling rate of 10 GS/s, the TX data rates are 3.33 Gb/and 6.67 Gb/s for QPSK and 16-QAM, respectively. Implemented in 40 nm bulk-CMOS, the core circuit occupies $0.18\text{mm}^{2}$ core of the $2.38\text{mm}^{2}$ total die area, and consumes 40.2 mW from a 0.9 V supply.

MrDP: m ultiple- r ow d etailed p lacement of heterogeneous-sized cells for advanced nodes

Abstract: As VLSI technology shrinks to fewer tracks per standard cell, e.g., from 10-track to 7.5-track libraries (and lesser for 7nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multi-bit flip-flops or flop trays to save power creates large cells that further complicate critical design tasks, such as placement. Detailed placement happens to be a key optimization transform, which is repeatedly invoked during the design closure flow to improve design parameters, such as, wirelength, timing, and local wiring congestion. Advanced node designs, with hundreds of thousands of multiple-row cells, require a paradigm change for this critical design closure transform. The traditional approach of fixing multiple-row cells during detailed placement and only optimizing the locations of single-row standard cells can no longer obtain appreciable quality of results. It is imperative to have new techniques that can simultaneously optimize both multiple- and single-row high cell locations during detailed placement. In this paper, we propose a new density-aware detailed placer for heterogeneous-sized netlists. Our approach consists of a chain move scheme that generalizes the movement of heterogeneous-sized cells as well as a nested dynamic programming based approach for wirelength and density optimization. Experimental results demonstrate the effectiveness of these techniques in wirelength minimization and density smoothing compared with the most recent detailed placer for designs with heterogeneous-sized cells.

A Methodology for Standard Cell Design for QCA

Abstract: QCA (Quantum-Dot Cellular Automata) is an emerging nanotechnology that has the potential to replace current CMOS technologies. QCA permits extremely low power consumption, since its working principle is not based on electric current flow but on Coulomb interaction. The development of Electronic Design Automation (EDA) tools and flows is an essential step towards the applicability of QCA for integrated designs. However, the scarce number of works in this field highlights that there is plenty of room for the development of new EDA methodologies for emerging nanotechnologies. Standard cells play an important role in this context, since the development of routing and placement algorithms are strongly related to their existence. This work presents a methodology for standard cell design for QCA as well as the exemplary QCA cell library ONE, which is based on the recently proposed USE (Universal, Scalar and Efficient) clocking scheme. Two representative case studies indicate the feasibility of the approach.

Design for manufacturability and reliability in extreme-scaling VLSI

Abstract: In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moores law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Abstract: In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

Yield Prediction With a New Generalized Process Capability Index Applicable to Non-Normal Data

Abstract: Monte Carlo (MC) techniques are widely applied to check a design on its robustness and for estimating the production yield of integrated circuits. Using standard random MC and the sample yield for estimation, a very large number of samples is required for accurate verification, especially if a high yield is desired. This can make MC extremely time consuming, but if the data follows a normal Gaussian distribution a much faster yield prediction is possible by using the well-known ${C}_{\text {PK}}$ method. We extended this specification-distance-based scheme for the far more difficult general non-normal case by three different means, ending up in a new generalized process capability index named ${C}_{\text {GPK}}$ . First, we apply parametric modeling only to the specification-sided distribution part. This way any difficulties in distribution parts that actually have little yield impact do not degrade the model fit anymore. Second, to improve the parametric model we introduce a new tail parameter ${t}$ . Third, to allow modeling of difficult asymmetrical, multimodal or flat distributions we also introduce a new reference location parameter instead of using the mean. An advantage of improving MC this way is that—in opposite to many other MC enhancements (like importance sampling)—the performance of the ${C}_{\text {GPK}}$ is not negatively impacted by design complexity. We described the formulation of the ${C}_{\text {GPK}}$ and derived confidence intervals using an advanced bootstrap scheme. We verified the performance against the sample yield and ${C}_{\text {PK}}$ for a representative set of distributions, including real production data and MC data from the design of a CMOS operational amplifier and other circuits.

ePlace-3D: Electrostatics based Placement for 3D-ICs

Abstract: We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) 3D numerical solution with improved spectral formulation (3) 3D nonlinear pre-conditioner for convergence acceleration (4) interleaved 2D-3D placement for efficiency enhancement. Our placer outperforms the leading work mPL6-3D and NTUplace3-3D with 6.44% and 37.15% shorter wirelength, 9.11% and 10.27% fewer 3D vertical interconnects (VI) on average of IBM-PLACE circuits. Validation on the large-scale modern mixed-size (MMS) 3D circuits shows high performance and scalability.

Comprehensive path based analysis process

Abstract: The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis (“PBA”) on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Mealtime Disruption and Caregiver Stress in Referrals to an Outpatient Feeding Clinic

Abstract: Background: This investigation explores the feeding behaviors, comorbidities, and parenting stress in young children referred to an outpatient feeding clinic. Materials and Methods: Eligible participants (n =72) were primary caretakers of children ages 2–6 years referred to an interdisciplinary outpatient feeding disorder clinic, subcategorized according to the absence (n = 18) or presence (n = 54) of caretaker-reported medical or developmental comorbidities. This group was compared with an equivalent control sample of caretakers of age-matched children (n = 72). Measures included the Children’s Eating Behavior Inventory (CEBI) and the Parenting Stress Index–Short Form (PSI-SF). Results: The CEBI and PSI scores were higher in the feeding disorder group than in the control group. PSI total was incrementally increased for control vs feeding disorder without comorbidity vs feeding disorder with comorbidity. Conclusion: Increased maladaptive behaviors and parenting stress were evident in children with feeding...

Methodology for analyzing and quantifying design style changes and complexity using topological patterns

Abstract: In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quantify and measure design changes and the degree of layout regularization. This new approach allows engineers to perform a full profiling across all patterns that exist in design and without needing to explicitly specify what patterns to analyze.

Echogenic pattern and medical articles including same

Abstract: A medical article, such as a needle, includes an echogenic portion The echogenic portion includes one or more patterns The one or more patterns can include closely spaced surface features which provide enhanced echogenicity The surface features can include grooves, recesses, channels, pits, pores, or the like The grooves can be arranged in a zigzag shape in a needle body of the medical article The zigzag shape can extend circumferentially around the needle body, that is, the grooves can extend perpendicularly to a longitudinal axis of the needle body The zigzag shape provides enhanced echogenicity regardless of the section of the needle body underlying the ultrasound beam in use

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions

Abstract: Modern systems-on-a-chip and microprocessors, e.g., those in smart phones and laptops, typically have multiple operating conditions, such as video streaming, Web browsing, standby, and so on. They will have different performance targets and run under different supply voltages. Gate sizing (with threshold voltage assignment) is a fundamental step for power/performance optimization. However, conventional gate sizing algorithms only consider one scenario, e.g., the performance-critical operating condition, which may be over-design for other operating conditions. In addition, reliability has become a prime concern in nanometer designs, and gate sizing has been employed to mitigate aging. However: 1) previous aging-affected delay models do not take into account more than one operating condition to estimate the aging impact and 2) earlier aging aware gate sizing algorithms only consider one operating condition at a time. In this paper, we present a new paradigm of aging aware gate sizing, one-size-fits-all (OSFA), which performs power/performance optimizations across multiple operating conditions. The existing delay model for negative bias temperature instability (NBTI) is extended to take into account multiple operating conditions, and incorporated into our OSFA framework. Based on OSFA, we also adjust the supply voltage targeting overall power optimization. A speed-up heuristic is proposed to scale our OSFA design space exploration methodology for higher number of operating conditions. Experimental results on industry-strength benchmarks demonstrate that: 1) compared with conventional approach OSFA could provide an average 6.1% reduction in power without performance loss; 2) NBTI-aware OSFA framework can provide significant improvement in comparison with guard-band based traditional NBTI-aware gate sizing approach; and 3) percentage savings compared to conventional methodology increases with the number of operating conditions.

Synuclein-γ (SNCG) expression in ovarian cancer is associated with high-risk clinicopathologic disease

Abstract: Synuclein gamma (SNCG) expression is associated with advanced disease and chemoresistance in multiple solid tumors. Our goal was to determine if SNCG protein expression in ovarian cancer was correlated with clinicopathologic variables and patient outcomes. Tissue microarrays from primary tumors of 357 ovarian, fallopian tube, and primary peritoneal cancer patients, who underwent primary surgery at Roswell Park Cancer Institute between 1995 and 2007, were immunohistochemically stained for SNCG. A pathologist blinded to patient data scored tumors as positive if ≥10 % of the sample stained for SNCG. Medical records were reviewed for clinicopathologic and demographic variables. Between the positive and negative groups, Wilcoxon rank-sum test was used to compare the median ages and Fisher’s exact test was used to compare groups in categorical variables. Cox proportional hazard models examined associations between SNCG and overall and progression-free survival. The median follow-up was 36 months, median overall survival was 39 months, and median progression-free survival was 18 months. SNCG presence was associated with clinical variables of serous histology, grade 3 disease, suboptimal debulking, ascites at surgery, FIGO stage III-IV cancer, or initial CA-125 level >485. There was no significant difference in overall survival (HR 1.06 95 % CI 0.81–1.39 P 0.69) or progression-free survival (HR 1.16 95 % CI 0.89–1.50 P 0.28) for patients with or without SNCG expression. SNCG expression in ovarian cancer is frequent in patients with high-risk features, but it does not correlate with chemotherapy response, overall survival, or progression-free survival.

Negotiation-based track assignment considering local nets

Abstract: Routability has become a very challenging issue in a modern VLSI design flow. Many works use global routing to estimate the routability in the early design stages. However, global routing cannot accurately capture local congestion, so it is hard to detect the detailed routability issue. To more accurately estimate the detailed-routing routability, this paper presents a track-assignment-based routability estimator. In this work, wire segments called iroutes are extracted from a global routing result, and then the proposed negotiation-based algorithm assigns these iroutes to proper tracks and minimizes the overlaps between the iroutes. Based on the assignment result, we can judge which regions may have critical routability issues by seeing where more overlaps reside.

Practical Validation of Bytecode to Bytecode JIT Compiler Dynamic Deoptimization

Abstract: Speculative inlining in just-in-time compilers enables many performance optimizations. However, it also introduces significant complexity. The compiler optimizations themselves, as well as the deoptimization mechanism are complex and error prone. To stabilize our bytecode to bytecode just-in-time compiler, we designed a new approach to validate the correctness of dynamic deoptimization. The approach consists of the symbolic execution of an optimized and an unop-timized bytecode compiled method side by side, deoptimizing the abstract stack at each deoptimization point (where dynamic deoptimization is possible) and comparing the deoptimized and unoptimized abstract stack to detect bugs. The implementation of our approach generated tests for several hundred thousands of methods, which are now available to be run automatically after each commit.

LRR-DPUF: learning resilient and reliable digital physical unclonable function

Abstract: Conventional silicon physical unclonable function (PUF) extracts fingerprints from transistor's analog attributes, which are vulnerable to environmental and operational variations. Recently, digitalized PUF prototypes have emerged to overcome the vulnerability issues, however, the existing prototypes are either hybrid of analog-digital PUFs which are still under the shadow of vulnerability, or impractical for real-world implementation. To address the above limitations, we propose a learning resilient and reliable digital PUF (LRR-DPUF). The fingerprints are extracted from VLSI interconnect geometrical randomness induced by lithography variations. Crucially, we use strongly skewed latches to ensure the immunity against environmental and operational variations. Further, a cross-coupled, highly non-linear logic network is proposed to effectively spread and augment even subtle interconnect randomness, as well as to achieve strong resilience to machine learning attacks. We demonstrate that a 64-bit LRR-DPUF exhibits close to ideal statistical performances, including 0 intra Hamming Distance. We also mathematically prove that each output of the LRR-DPUF follows uniform distribution. Various state-of-the-art machine learning models show almost no better than random prediction accuracies when applied to LRR-DPUF.

Electrical/thermal co-design and co-simulation, from chip, package, board to system

Abstract: It has been well known for years that as the critical feature size within a chip keeps shrinking, design and optimization among power, heat and performance would become even challenging. On one hand, the electrical functionalities of the devices are closely coupled with temperature and power distributions. On the other hand, the devices within the chip are not totally isolated and confined — the connection and interaction with the environments such as the package, board, and enclosure cannot be ignored especially from the heat transport perspective. Simulation tools in electronic design automation have to satisfy the requirement of electrical/thermal co-simulation for advanced electronic systems having a wide range of critical sizes, and provide efficient approaches with accurate data for design optimization. This is the main purpose of this paper, and we introduce a portfolio of tools to facilitate electrical/thermal co-simulation from chip, package, board to system.

Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off

Abstract: Public-key cryptosystems such as RSA have been widely used to secure digital data in many commercial systems. Modular arithmetic on large operands used during modular exponentiation makes RSA computationally challenging. Traditionally, software implementations of these algorithms provided the highest flexibility but lacked performance. On the contrary, custom hardware accelerators provided the highest performance but lacked flexibility and adaptability to changing algorithms, parameters, and key sizes. In this paper, we present a hardware/software codesign of RSA cryptosystem that improves performance, while retaining flexibility. We adopted Xilinx Zynq-7000 SoC platform, which integrates a dual-core ARM Cortex-A9 processing system along with Xilinx programmable logic. The software part of our implementation is based on RELIC library (Efficient Library for Cryptography). The performance vs. flexibility trade-off is investigated, and the speed-up of our codesign implementation vs. the purely software implementation of RSA on the same platform is reported. Our results show a speedup of up to 57 times when compared with the software implementation for 2048-bit operand size. We also propose a generic model for HW/SW codesign focused on flexibility with comparable performance to existing HW/SW implementations.

A tensor-based volterra series black-box nonlinear system identification and simulation framework

Abstract: Tensors are a multi-linear generalization of matrices to their d-way counterparts, and are receiving intense interest recently due to their natural representation of high-dimensional data and the availability of fast tensor decomposition algorithms. Given the input-output data of a nonlinear system/circuit, this paper presents a non-linear model identification and simulation framework built on top of Volterra series and its seamless integration with tensor arithmetic. By exploiting partially-symmetric polyadic decompositions of sparse Toeplitz tensors, the proposed framework permits a pleasantly scalable way to incorporate high-order Volterra kernels. Such an approach largely eludes the curse of dimensionality and allows computationally fast modeling and simulation beyond weakly non-linear systems. The black-box nature of the model also hides structural information of the system/circuit and encapsulates it in terms of compact tensors. Numerical examples are given to verify the efficacy, efficiency and generality of this tensor-based modeling and simulation framework.

Practical public PUF enabled by solving max-flow problem on chip

Abstract: The execution-simulation gap (ESG) is a fundamental property of public physical unclonable function (PPUF), which exploits the time gap between direct IC execution and computer simulation. ESG needs to consider both advanced computing scheme, including parallel and approximate computing scheme, and IC physical realization. In this paper, we propose a novel PPUF design, whose execution is equivalent to solving the hard-to-parallel and hard-to-approximate max-flow problem in a complete graph on chip. Thus, max-flow problem can be used as the simulation model to bound the ESG rigorously. To enable an efficient physical realization, we propose a crossbar structure and adopt source degeneration technique to map the graph topology on chip. The difference on asymptotic scaling between execution delay and simulation time is examined in the experimental results. The measurability of output difference is also verified to prove the physical practicality.

ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite

Abstract: Boolean Matching is significant to industry applications, such as library binding, synthesis, engineer change order, and hardware Trojan detection. Instead of basic Boolean matching, Non-exact Projective NPNP Boolean Matching allows to match two designs by not only negating and permuting inputs/outputs but also merging them or binding constants to inputs. Besides, the matching goal is extended to achieve the largest number of output equivalences between two designs. This kind of Boolean matching may get better quality in the related applications due to more flexibility and scalability, and the development of its algorithms is more challengeable. Hence, this problem has some research values. In ICCAD 2016 CAD contest, given two designs, participants need to decide how to permute, negate and merge designs' inputs/outputs or bind constants for achieving largest number of output equivalences. The score will be evaluated by how many outputs are equivalent and the runtime. We expect the contest result can improve industry applications and bring more research interests.

Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing

Abstract: At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.

Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact

Abstract: A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.

Tunable impedance circuit for a transmitter output stage

Abstract: A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one of the resistors, thereby calibrating the impedance cell. The output impedance can be set by identifying a combination of calibrated impedance cells that need to be activated in order to produce the target output impedance.

A Novel and Scalable Design Methodology for the Simulation of Photonic Integrated Circuits

Abstract: We present a novel design methodology for silicon photonic integrated circuits (PIC) that integrates Cadence's Spectre with Lumerical's INTERCONNECT. It supports parametric analysis of bidirectional, multi-mode PICs, with electrical feedback.

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Stitch aware detailed placement for multiple e-beam lithography

Abstract: As a promising candidate for next generation lithography, multiple e-beam lithography (MEBL) is able to improve manufacturing throughput using parallel beam printing. In MEBL, a layout is split into stripes and the layout patterns are cut by stripe boundaries, then all the stripes are printed in parallel. If a via pattern or a vertical long wire is overlapping with a stitch, it may suffer from poor printing quality due to the so called stitch error; then the circuit performance may be degraded. In this paper, we propose a comprehensive study on the stitch aware detailed placement to simultaneously minimize the stitch error and optimize traditional objectives, e.g., wirelength and density. Experimental results show that our algorithms are very effective on modified ICCAD 2014 benchmarks that zero stitch error is guaranteed while the scaled half-perimeter wirelength is very comparable to a state-of-the-art detailed placer.