Showing papers by "Freescale Semiconductor published in 2011"

Power Efficiency and Linearity Enhancement Using Optimized Asymmetrical Doherty Power Amplifiers

Abstract: This paper investigates the virtues of the asymmetrical Doherty power amplifier (PA) for improving the average power efficiency, linearity, and peak envelope power. It commences with an in-depth study of the effects of increasing the size of the peaking amplifier's transistor and its conduction angle on the Doherty PA's RF performance. In particular, the impact of the extended current profile of the peaking amplifier and reduced turn-on effects on the soft-turn characteristic are thoroughly analyzed, and their impacts on the average efficiency and peak power are deduced. Furthermore, the aggravation of the memory effects that accompany the gm3-based nonlinear distortion cancellation is experimentally demonstrated. Two asymmetrical Doherty PAs prototypes are fabricated using 80 W and 150 W laterally diffused metal oxide semiconductor field-effect transistors to individually improve average efficiency and linearity. When driven with a four carrier wideband code division multiple access (4C-WCDMA) signal, the asymmetrical Doherty PA allowed for excellent drain efficiency of approximately 50%, along with high linearity of approximately -50 dBc , using a memory polynomial digital predistorter at an average output power of 50 W. To the best of the authors' knowledge, this achieved efficiency is the highest reported in the literature for a high-power Doherty PA implemented in LDMOS technology.

Integrated circuit device and method for determining an index of an extreme value within an array of values

Abstract: An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.

Stacked semiconductor devices

Abstract: A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.

A Low-Power Low-Noise Dual-Chopper Amplifier for Capacitive CMOS-MEMS Accelerometers

Abstract: This paper reports a novel dual-chopper amplifier (DCA) and its application to monolithic complementary metal-oxide semiconductor-microelectromechanical systems accelerometers. The DCA design minimizes the power consumption and noise by chopping the sensing signals at two clocks. The first clock is a high frequency for removing the flicker noise while the second clock is a significantly lower frequency to keep the unit gain bandwidth low. A monolithic three-axis accelerometer integrated with the DCA on the same chip has been successfully fabricated using a post-CMOS micromachining process. The measured noise floors are 40 μ g/√Hz in the x - and y -axis and 130 μ g/√Hz in the z -axis, and the power consumption is about 1 mW per axis.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Abstract: We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

Multiple core data processor with usage monitoring

Abstract: A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.

Method and Apparatus for Snoop-and-Learn Intelligence in Data Plane

Abstract: An approach is provided where incoming packets are received at a data plane and header fields are extracted from the incoming packet. Flows from a flow data store are matched with the extracted header fields from the incoming packet. Packet descriptor data associated with the incoming packet is marked in the selected incoming packet forming a marked ingress packet with marking performed when the matching fails. The marked ingress packet is forwarded to a control plane that retrieves flow-related data related to the marked ingress packet and updates the marked packet descriptor data using the retrieved flow-related data, thereby forming an updated marked packet. The control plane passes the updated marked packet back to the data plane for further processing to update the flow data stored in the flow data store.

On the Precoder Design of Flat Fading MIMO Systems Equipped With MMSE Receivers: A Large-System Approach

Abstract: This paper is devoted to the design of precoders maximizing the ergodic mutual information (EMI) of bi-correlated flat fading MIMO systems equipped with MMSE receivers. The channel state information and the second-order statistics of the channel are assumed available at the receiver side and at the transmitter side respectively. As the direct maximization of the EMI needs the use of nonattractive algorithms, it is proposed to optimize an approximation of the EMI, introduced recently, obtained when the number of transmit and receive antennas t and τ converge to ∞ at the same rate. It is established that the relative error between the actual EMI and its approximation is a O( [ 1/( t2)]) term. It is shown that the left singular eigenvectors of the optimum precoder coincide with the eigenvectors of the transmit covariance matrix, and its singular values are solution of a certain maximization problem. Numerical experiments show that the mutual information provided by this precoder is close from what is obtained by maximizing the true EMI, but that the algorithm maximizing the approximation is much less computationally intensive.

Scheduling memory access requests using predicted memory timing and state information

Abstract: A data processing system (100) employs an improved arbitration process (600) in selecting pending memory access requests received from the one or more processor cores (11) for servicing by the memory (16). The arbitration process uses memory timing and state information (401) pertaining both to memory access requests (300, 501) already submitted to the memory for servicing and to the pending memory access requests (300, 501) which have not yet been selected for servicing by the memory (16). The memory timing and state information (401) may be predicted memory timing and state information; that is, the component (14) of the data processing system (100) that implements the improved scheduling algorithm (600) may not be able to determine the exact point in time at which a memory controller (15) initiates a memory access for a corresponding memory access request and thus the component (14, 304) maintains information that estimates or otherwise predicts the particular state of the memory (16) at any given time.

Packaging process to create wettable lead flank during board assembly

Abstract: A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

The Head of the Class

Abstract: Any time a person uses a wireless communications device, the equipment will always have some sort of power amplifier (PA) on board to boost the low-level analog signal to a level suitable to maintain adequate signal-to-noise ratio (SNR) over the communication link. There are a variety of applications (and many more to come in the future) requiring PAs of various power levels.

Automotive radar system and method for using same

Abstract: A radar system (44) for a vehicle (42) includes a transmit unit (56) and a receive unit (58). The transmit unit (56) includes a single beam antenna (72) for output of a radar signal (74) into a target zone (46). The receive unit (58) includes a single beam antenna (76) for receiving a direct receive signal (78) and an indirect receive signal (80). The receive signals (78, 80) are reflections of the radar signal (74) from an object (34, 36) in the target zone (46). The indirect receive signal (80) is reflected off the object (34, 36) toward a reflective panel (54) of the vehicle (42), and the indirect receive signal (80) is reflected off the reflective panel (54) for receipt at the receive antenna (76). The receive signals (78, 80) are summed to produce a detection signal (81) indicating presence of the object (34, 36) in the target zone (46).

Non-volatile memory and logic circuit process integration

Abstract: A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polysilicon layer is formed over the NVM region and removing the first polysilicon layer over the logic region. A dielectric layer is formed over the NVM region including the first polysilicon layer and over the logic region. A protective layer is formed over the dielectric layer. The dielectric layer and the protective layer are removed from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region. A high-k dielectric layer is formed over the logic region and the remaining portion of the protective layer. A first metal layer is formed over the high K dielectric layer. The first metal layer, the high K dielectric, and the remaining portion of the protective layer are removed over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high K dielectric layer over the logic region. A conductive layer is deposited over the remaining portion of the dielectric layer and over the first metal layer. The NVM cell and the logic transistor are formed and this includes patterning the conductive layer.

Ldo linear regulator with improved transient response

Abstract: An LDO regulator system has first and second current mirror circuits connected to its output terminal. A load attached to the output terminal is supplied with a constant voltage. Variations in the load that cause variations in the magnitude of the output voltage trigger one of the first or second current mirror circuits to generate a current that varies the magnitude of a gate voltage of a pass-transistor. The variation in the gate voltage in turns varies the drain current of the pass-transistor, which varies the output voltage to counter the change in the magnitude of the output voltage. Using the first and second current mirror circuits avoids the need for a large load capacitor and very high bandwidth of a conventional LDO regulator.

Object detection device with variable sensitivity electric field measurement circuit

Abstract: Three or more electrodes are arranged on either a window frame or window glass of an automobile. An electric field measurement unit measures the capacitance between various combinations of the electrodes to detect whether an object is located between the window frame and window glass. A control circuit varies the sensitivity of the electric field measurement unit by switching amongst the electrodes used for capacitance measurement based on the movement and position of the window glass.

Customized shield plate for a field effect transistor

Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Getting More From the Semiconductor Test: Data Mining With Defect-Cluster Extraction

Abstract: High-volume production data shows that dies, which failed probe test on a semiconductor wafer, have a tendency to form certain unique patterns, i.e., defect clusters. Identifying such clusters is one of the crucial steps toward improvement of the fabrication process and design for manufacturing. This paper proposes a new technique for defect-cluster identification that combines data mining with a defect-cluster extraction using a Segmentation, Detection, and Cluster-Extraction algorithm. It offers high defect-extraction accuracy, without any significant increase in test time and cost.

Next smart sensors generation

Abstract: Smart sensors are defined by the IEEE 1451 standard as sensors with small memory and standardized physical connection to enable the communication with processor and data network. Beyond this definition, smart sensors are defined as the combination of a sensor with signal conditioning, embedded algorithms and digital interface. They are currently highly adopted in mobile and portable devices like phones and tablets. Such types of sensors respond to the issues of power consumption, data communication and system integration at the sensor level and for predefined use cases. Some limitations of smart sensors are the lack of flexibility, absence of customization, narrow spectrum of applications, and the basic communication protocol. Moreover, there is a growing request of new and broader applications for individual sensors while integrating an increasing number of different types of sensors. Therefore, to overcome these limitations and address the new challenges, the next generation of sensors is proposed: the intelligent sensor platform. It is defined as the combination of sensor and processing with a dedicated architecture to aggregate external sensor data. The main advantages are reviewed and an implementation of an intelligent sensor platform embedding a MEMS accelerometer with a 32-bit microcontroller is described.

Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package The free end of signal conduits is exposed while the other end remains coupled to a lead frame The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads

Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

Abstract: We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter.

Multiple function power domain level shifter

Abstract: A level shifter including input and output power nodes, input and output reference nodes, input and output signal nodes, and a lever shifter network. The input power and input reference nodes operate within a first power domain and the output power and output reference nodes operate within a second power domain. The level shifter network receives an input signal operable within the first power domain, performs voltage shifting between the input and output power nodes and between the input and output reference nodes, and provides an output signal output signal indicative of the input signal that operates within the second power domain. The level shifter may include power and/or ground bypass such that either one or both of power and ground voltage shifting may be bypassed for faster switching. The level shifter may include an isolation input to assert the output to a known level.

Mram device and method of assembling same

Abstract: A method of assembling a magnetoresistive random access memory (MRAM) device includes providing a substrate having an opening. A tape is applied to a surface of the substrate and a first magnetic shield is placed onto the tape and within the substrate opening. An adhesive is applied between the first magnetic shield and the substrate to attach the first magnetic shield to the substrate. An MRAM die is attached to the first magnetic shield and bond pads of the MRAM die are connected to pads on the substrate with wires. A second magnetic shield is attached to a top surface of the MRAM die. An encapsulating material is dispensed onto the substrate, the MRAM die, the second magnetic shield and part of the first magnetic shield, cured, and then the tape is removed. Solder balls then may be attached to the substrate.

Mems sensor with folded torsion springs

Abstract: A microelectromechanical systems (MEMS) sensor ( 40 ) includes a substrate ( 46 ) and a suspension anchor ( 54 ) formed on a planar surface ( 48 ) of the substrate ( 46 ). A first folded torsion spring ( 58 ) and a second folded torsion spring ( 60 ) interconnect the movable element ( 56 ) with the suspension anchor ( 54 ) to suspend the movable element ( 56 ) above the substrate ( 46 ). The folded torsion springs ( 58, 60 ) are each formed from multiple segments ( 76 ) that are linked together by bar elements ( 78 ) in a serpentine fashion. The folded torsion springs ( 58, 60 ) have an equivalent shape and are oriented relative to one another in rotational symmetry about a centroid ( 84 ) of the suspension anchor ( 54 ).

Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints

Abstract: Although the stacking of multiple strata to produce three-dimensional (3D) integrated circuits (ICs) improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge owing to the increased power density. There is a need for design tools to understand and optimise the trade-off between electrical and thermal design at the device and block levels. This study presents results from thermal-electrical co-optimisation for block-level floorplanning in a multi-die 3D IC under various manufacturing and physical design constraints. A method for temperature computation based on linearity of the governing energy equation is presented. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimise both the maximum temperature and the interconnect length. It is shown that co-optimisation of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Physical design constraints because of cost-effective 3D manufacturing such as using fully or partly identical dies using reciprocal design symmetry (RDS), differentiated technology in each die and thinned die/wafer are discussed and their impact on the thermal-electrical co-optimisation is investigated. In some cases, the cheapest manufacturing choice, such as using identical die, for each layer may not result in optimal thermal and electrical design. Results presented in this work highlight the need for thermal and electrical co-design in multi-strata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D ICs.

MEMS Device With Enhanced Resistance to Stiction

Abstract: A MEMS device ( 20 ) includes a substrate ( 24 ) and a movable element ( 22 ) adapted for motion relative to the substrate ( 24 ) A secondary structure ( 46 ) extends from the movable element ( 22 ) The secondary structure ( 46 ) includes a secondary mass ( 54 ) and a spring ( 56 ) interconnected between the movable element ( 22 ) and the mass ( 54 ) The spring ( 56 ) is sufficiently stiff to prevent movement of the mass ( 54 ) when the movable element ( 22 ) is subjected to force within a sensing range of the device ( 20 ) When the device ( 20 ) is subjected to mechanical shock ( 66 ), the spring ( 56 ) deflects so that the mass ( 54 ) moves counter to the motion of the movable element ( 22 ) Movement of the mass ( 54 ) causes the movable element ( 22 ) to vibrate to mitigate stiction between the movable element ( 22 ) and other structures of the device ( 20 ) and/or to prevent breakage of components within the device ( 22 )

Sensor device with sealing structure

Abstract: Apparatus and related fabrication methods are provided for a sensor device. The sensor device includes a sensor structure including a first portion having a sensing arrangement formed thereon and a second structure. A sealing structure is interposed between the sensor structure and the second structure, wherein the sealing structure surrounds the first portion of the sensor structure. The sealing structure establishes a fixed reference pressure on a first side of the first portion, and an opposing side of the first portion is exposed to an ambient pressure.

ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

Abstract: Electrostatic discharge (ESD) failure is a major reliability problem, and ESD protection is an emerging design challenge for radio-frequency (RF) integrated circuits demanding extremely high reliability for wireless applications in harsh environments. This paper reports the design and optimization of a 5-kV ESD-protected 2.4-GHz power amplifier (PA) circuit in a 0.18-μm RFCMOS technology. A new mixed-mode ESD simulation-design method and an accurate RF ESD characterization technique are used to minimize the inevitable ESD-induced parasitic effects, which can significantly degrade PA circuit performance. A novel ESD-aware PA design technique is utilized to optimize whole-chip ESD+PA performance. Experiments show that conventional ESD protection can seriously affect the PA circuit, while optimized ESD protection may resolve such a problem. The optimized ESD-protected PA circuit achieves good whole-chip performance, including 5-kV ESD protection, a linear output of 13.5 dBm, a gain of 20.2 dB, and a power-added efficiency of ~ 18%, all favorable in the same design category.

Surface and buried interfacial structures of epoxy resins used as underfills studied by sum frequency generation vibrational spectroscopy.

Abstract: Flip chip technology has greatly improved the performance of semiconductor devices, but relies heavily on the performance of epoxy underfill adhesives. Because epoxy underfills are cured in situ in flip chip semiconductor devices, understanding their surface and interfacial structures is critical for understanding their adhesion to various substrates. Here, sum frequency generation (SFG) vibrational spectroscopy was used to study surface and buried interfacial structures of two model epoxy resins used as underfills in flip chip devices, bisphenol A digylcidyl ether (BADGE) and 1,4-butanediol diglycidyl ether (BDDGE). The surface structures of these epoxies were compared before and after cure, and the orientations of their surface functional groups were deduced to understand how surface structural changes during cure may affect adhesion properties. Further, the effect of moisture exposure, a known cause of adhesion failure, on surface structures was studied. It was found that the BADGE surface significantly restructured upon moisture exposure while the BDDGE surface did not, showing that BADGE adhesives may be more prone to moisture-induced delamination. Lastly, although surface structure can give some insight into adhesion, buried interfacial structures more directly correspond to adhesion properties of polymers. SFG was used to study buried interfaces between deuterated polystyrene (d-PS) and the epoxies before and after moisture exposure. It was shown that moisture exposure acted to disorder the buried interfaces, most likely due to swelling. These results correlated with lap shear adhesion testing showing a decrease in adhesion strength after moisture exposure. The presented work showed that surface and interfacial structures can be correlated to adhesive strength and may be helpful in understanding and designing optimized epoxy underfill adhesives.

Logic and non-volatile memory (NVM) integration

Abstract: A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

Methods for fabricating sensor device package using a sealing structure

Abstract: Fabrication methods are provided for a sensor device packages. An exemplary fabrication method involves bonding a sensor structure and another structure using a sealing structure. The sealing structure surrounds a diaphragm region of the sensor structure and provides an airtight seal between the sensor structure and the other structure to establish a fixed reference pressure on one side of the diaphragm region.