Xilinx

About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).

Programmable shift register

Abstract: A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length. The mode control circuit is programmable such that the shift register loads an initial operating state, or to implements bi-directional (count up/down) control. Some of the I/O lines of the programmable interconnect circuit are connected to the next-state control circuit. The next-state control circuit includes a sequence circuit, a maximal count circuit and a skip-state circuit, all of which are programmable to utilize the output signals from the flip-flops that are transmitted on the first bus.

Programmable logic expander

Abstract: A programmable logic device that provides an AND gate array connected to an OR gate array connected to a third logic level, a logic expander module. The module provides programmable selection of any of 16 one- and two-variable logic functiosn or any of 256 one-, two- and three-variable logic functions. In one embodiment, the invention uses logic function gates such as AND, OR, XOR and inverter gates to form the logic functions. In a second embodiment and a third embodiment, a look-up table and an array of pass transistors, respectively, are used to form the logic functions.

Load programmable output buffer.

Abstract: The present invention reduces bounce in the power (VCC) or ground (VSS) supply voltages of an integrated circuit chip by gradually turning output drivers (407b) both on and off, so there is not a sharp discontinuity in current flow to an external device (PAD). Greatest current flow occurs at the middle of a transition period. The gradual turn-off at the end of a transition is achieved by feeding back voltage of the output signal (408) to a device (501) which controls the output driver (407b). As output voltage approaches its final value, the output driver (407b) gradually turns off, preventing a sharp transient in the power (VCC) or ground (VSS) voltage of the integrated circuit chip.

Antifuse-based programmable logic circuit

Abstract: The present invention provides a programmable logic circuit including a first set of lines coupled to a logic module, a second set of lines, and a plurality of transistors. Each transistor in the array has a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to one of the first set of lines and the second terminal is coupled to one of the second set of lines. In accordance with the present invention, an antifuse is coupled between the third terminal of the transistor and a voltage source. By selectively programming antifuses in the array and selectively turning on transistors, complex user functions with a large number of inputs are implemented in one pass.

Error detection structure and method using partial polynomial check

Abstract: The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session The subset transmitted also preferably has this property A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session