Xilinx

About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).

FPGA Implementation of Carrier Synchronization for QAM Receivers

Abstract: Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. While there are a number of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and flexibility. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper examines carrier synchronization in SDRs using FPGA based signal processors. We provide a tutorial style overview of carrier recovery techniques for QPSK and QAM modulation schemes and report on the design and FPGA implementation of a carrier recovery loop for a 16-QAM modern. Two design alternatives are presented to highlight the rich design space accessible using configurable logic. The FPGA device utilization and performance for a carrier recovery circuit using a look-up table approach and CORDIC arithmetic are presented. The simulation and FPGA implementation process using a recent system level design tool called System Generator™ for DSP described.

Shadow DRAM for programmable logic devices

Abstract: A plurality of DRAM cells are used to store the state of the programmable points in the FPGA ("FPGA DRAM cells"). A shadow DRAM array holds duplicate data of the plurality of DRAM cells. A DRAM cell of the shadow DRAM array is sensed during a refresh cycle. In this manner the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell.

Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication

Abstract: A polar transmitter (TX) is implemented at 60 GHz, enabling a power amplifier (PA) to operate in saturation where efficiency is highest, even when handling higher order modulations such as QPSK and 16-QAM. The phase path is upconverted by I-Q mixers, while the amplitude path modulates an RF-DAC. Aimed at 802.11ad applications, the 10 GS/s (i.e., 6x-oversampled) polar TX realizes more than 30 dB alias attenuation, and the input bandwidth exceeds 3.1 GHz. The PA saturated output power is 10.8 dBm with 29.8% drain efficiency at the maximum RF-DAC code. Average output power is 8.1 dBm with 22.3% drain efficiency at $-20.7\;\text{dB}$ EVM for QPSK modulation without RF-DAC predistortion. The corresponding 16-QAM values are: 7.2 dBm average output power with 19.8% efficiency at $-16.5\;\text{dB}$ EVM. With predistortion, a QPSK modulated output achieves 5.3 dBm average power with 15.3% efficiency at $-23.6\;\text{dB}$ EVM, while 3.6 dBm average power with 11.6% efficiency at $-18.1\;\text{dB}$ EVM is realized for 16-QAM. For a sampling rate of 10 GS/s, the TX data rates are 3.33 Gb/and 6.67 Gb/s for QPSK and 16-QAM, respectively. Implemented in 40 nm bulk-CMOS, the core circuit occupies $0.18\text{mm}^{2}$ core of the $2.38\text{mm}^{2}$ total die area, and consumes 40.2 mW from a 0.9 V supply.

Programmable logic device with configurable power supply

Abstract: An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexer that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Tunable clock distribution system for reducing power dissipation

Abstract: A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.