Institution
Xilinx
Company•San Jose, California, United States•
About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).
Topics: Programmable logic device, Integrated circuit, Field-programmable gate array, Signal, Circuit design
Papers published on a yearly basis
Papers
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10 Oct 1994TL;DR: Field programmable gate arrays (FPGAs) combine the high-integration benefits of gate arrays with the time-to-market benefits of a user-programmable device.
Abstract: Field programmable gate arrays (FPGAs) combine the high-integration benefits of gate arrays with the time-to-market benefits of a user-programmable device. Already a mainstream logic technology, the growth rate of FPGA usage will continue to exceed that of other ASIC technologies. FPGA technology is having a major impact on electronic system design, especially through the use of FPGAs as reconfigurable computing elements. >
57 citations
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12 Mar 1993TL;DR: A modified partitioning method for placement of a circuit design into a programmable integrated circuit device having a specific distribution of physical resources along a horizontal or vertical line in the device was proposed in this article.
Abstract: A modified partitioning method for placement of a circuit design into a programmable integrated circuit device having a specific distribution of physical resources along a horizontal or vertical line in the device. The circuit design includes a plurality of circuit elements, for example three-state buffers which feed a common bus, or registers which receive a common clock signal. Such elements should or must be placed along a single horizontal or vertical line. One method includes the step of weighting connecting lines (nets) which join circuit elements to be placed along a common line with different weights for the horizontal and vertical directions. Alternatively, elements to be placed along the line are marked to be kept in line during partitioning. A min-cut algorithm then tends to or is required to avoid separating particular elements from a common line. The group containing the circuit elements with the line requirement is then partitioned such that the area and location of the group corresponds to the horizontal or vertical line.
57 citations
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27 Mar 2002TL;DR: In this paper, a method of and apparatus for generating a spread spectrum clock signal on an integrated circuit is presented. But the method is not suitable for the use of a fixed voltage source, and it cannot be implemented with a unity gain amplifier.
Abstract: A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.
57 citations
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09 Dec 2003TL;DR: In this article, a system and method for adding reconfigurable computational instructions to a reduced instruction set computer is presented, where a computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the core of the computer.
Abstract: A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.
56 citations
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14 Oct 1997TL;DR: In this paper, a tree-structured bus line with a plurality of multiplexers or gates is proposed for driving a bus line that is both fast and small, and the symmetrical delay of a tree structure minimizes the greatest delay.
Abstract: According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.
56 citations
Authors
Showing all 2816 results
Name | H-index | Papers | Citations |
---|---|---|---|
Jason Cong | 76 | 594 | 24773 |
Jonathan Rose | 58 | 187 | 15223 |
Ashutosh Sabharwal | 57 | 355 | 17926 |
Christoph Studer | 55 | 345 | 11694 |
Stephen M. Trimberger | 53 | 211 | 8806 |
Rodney Anthony Stewart | 51 | 313 | 7191 |
John C. McGrath | 49 | 291 | 13189 |
Sean A. Kelly | 48 | 93 | 11554 |
Song Han | 48 | 134 | 28364 |
Joseph R. Cavallaro | 44 | 374 | 7545 |
Krishna R. Narayanan | 44 | 269 | 6904 |
Farid N. Najm | 43 | 188 | 7530 |
Bernard J. New | 42 | 94 | 4562 |
Mehdi B. Tahoori | 41 | 394 | 6500 |
Steven P. Young | 38 | 181 | 5019 |