Xilinx

About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).

Method and system for device-level simulation of a circuit design for a programmable logic device

Abstract: A method and system for simulating a circuit design for a programmable logic device (PLD) at the device level. The same configuration data that is used to configure a PLD is used to generate objects that represent configurable logic elements of the PLD. During simulation, events are generated based on changes in output signal states of the objects. Each event includes an input signal state and identifies an object to which the input signal is to be applied. Since configurable logic elements are simulated, for example, lookup tables, instead of logic gates, fewer events need to be generated and processed than in a conventional simulator. In another embodiment, the system supports an interface that allows tools to interface with the simulator in the same manner as the tools interface with a PLD.

Method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit

Abstract: A method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit. A circuit design is first captured and converted into a first representation of the circuit design. The first representation is for programming a programmable logic device. A first part of the first representation is for programming a configurable element in the programmable logic device. The first part of the first representation is used as a set of parameters for a general model of the configurable element. The second representation of the circuit includes the parameterized general model of the configurable element.

An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs

Abstract: Triple Modular Redundancy (TMR) is recognized as one of the possible solutions to harden circuits implemented on SRAM-based FPGAs against soft-errors affecting configuration memory and user memory. Several works already showed cross-section figures confirming the soundness of TMR principle, however some faults still escape the TMR's fault masking mechanism. In this work we analyzed by means of extensive fault-injection experiments the TMR architecture. We identified some of the causes that are responsible for the escaped faults, and we proposed possible solutions. In our analyses we considered both the TMR and one of its enhanced version, the XTMR

Design of High Efficiency Integrated Voltage Regulators with Embedded Magnetic Core Inductors

Abstract: Integrated voltage regulators (IVRs) are one of the main trends in power delivery networks (PDNs) for electronic systems. A major challenge in the IVR design is to achieve sufficient integration / minimization of the required passive components of the IVR while still maintaining high power efficiency. This paper demonstrates that a buck converter type IVR designed with package embedded magnetic core inductors can achieve a very high efficiency with a substantially reduced area requirement compared to "air core" inductors. For the final design, an analytical evaluation shows 91% power efficiency for a 1.7V:1.05V conversion. Moreover, a stacked topology of the power stage allows a direct 5V:1V conversion at 79.4% efficiency eliminating the need for a separate off-package voltage regulator.

Structure and method for manually controlling automatic configuration in an integrated circuit logic block array

Abstract: Highly integrated programmable arrays, in which a logic array integrated circuit chip is divided into configurable logic blocks interconnected by configurable interconnect lines, have been programmed by automatic means and methods. The present invention provides for allowing a user to manually specify the partitioning of a logic design, and to allow a user to retain portions of a previously partitioned, placed, and routed design when making revisions. To allow for manual control of partitioning, a library of symbols includes a partitioning symbol that specifies which primitive logic functions can be grouped. The user specifies which ports of primitive logic functions will correspond with ports on the logic block symbol. The present invention also allows for partitioning parts of a design before combining the parts.