Institution
Xilinx
Company•San Jose, California, United States•
About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).
Topics: Programmable logic device, Integrated circuit, Field-programmable gate array, Signal, Circuit design
Papers published on a yearly basis
Papers
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11 Jul 2000TL;DR: In this paper, the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process is measured by comparing the oscillation frequencies of identical oscillators formed in different regions of the integrated circuit.
Abstract: Described are systems and methods for measuring the size uniformity of circuit features defined by the critical dimension of an integrated-circuit fabrication process. An integrated circuit is configured to include a number of oscillators, each occupying a region of the integrated circuit. Each oscillator oscillates at a frequency that depends on the critical dimension of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by comparing the oscillation frequencies of identical oscillators formed in various regions of the integrated circuit. In programmable logic devices, oscillators can be implemented using programmable logic resources. In other embodiments, small, simple oscillators can be placed at various locations on the integrated circuit.
46 citations
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01 Feb 1999TL;DR: Run-Time Parameterizable or RTP Cores which are an extension of the traditional static core model which permits run-time parameterization of designs and adds flexibility and portablilty unavailable in existing design environments.
Abstract: As FPGAs have increased in density, the demand for predefined intellectual property has risen. Rather than re-invent commonly used circuitry, libraries of standard parts have become available from a variety of sources. Currently, all of these offerings are based on the standard ASIC design flow and are used to produce fixed designs. This paper discusses Run-Time Parameterizable or RTP Cores which are an extension of the traditional static core model. Written in the Java (tm) programming language, RTP Cores are created at run-time and may be used to dynamically modify existing circuitry. In addition to providing support for run-time reconfigurable computing, RTP Cores permit run-time parameterization of designs. This adds flexibility and portablilty unavailable in existing design environments.
46 citations
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16 Apr 199146 citations
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11 Apr 1996TL;DR: In this paper, a programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production is presented.
Abstract: A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.
46 citations
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01 Oct 2004TL;DR: In this article, a method and apparatus for decoding configuration data is described, where a programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface.
Abstract: Method and apparatus for decoding configuration data is described. A programmable logic device having a configuration interface is coupled to boot memory coupled at the configuration interface. The boot memory contains boot cores for configuring the programmable logic device via the configuration interface. The boot cores include a configuration decoder core and an internal processor interface core. The boot cores may further include a processor core. The configuration decoder core provides a peripheral interface internal to the programmable logic device, and the boot memory contains at least one set of instructions for decoding encoded data and at least one library for writing decoded encoded data to configuration memory of the programmable logic device. The encoded data is obtained from data memory via the peripheral interface.
46 citations
Authors
Showing all 2816 results
Name | H-index | Papers | Citations |
---|---|---|---|
Jason Cong | 76 | 594 | 24773 |
Jonathan Rose | 58 | 187 | 15223 |
Ashutosh Sabharwal | 57 | 355 | 17926 |
Christoph Studer | 55 | 345 | 11694 |
Stephen M. Trimberger | 53 | 211 | 8806 |
Rodney Anthony Stewart | 51 | 313 | 7191 |
John C. McGrath | 49 | 291 | 13189 |
Sean A. Kelly | 48 | 93 | 11554 |
Song Han | 48 | 134 | 28364 |
Joseph R. Cavallaro | 44 | 374 | 7545 |
Krishna R. Narayanan | 44 | 269 | 6904 |
Farid N. Najm | 43 | 188 | 7530 |
Bernard J. New | 42 | 94 | 4562 |
Mehdi B. Tahoori | 41 | 394 | 6500 |
Steven P. Young | 38 | 181 | 5019 |