Xilinx

About: Xilinx is a company organization based out in San Jose, California, United States. It is known for research contribution in the topics: Programmable logic device & Integrated circuit. The organization has 2814 authors who have published 5275 publications receiving 91373 citations. The organization is also known as: Xilinx, Inc. & Xilinx (United States).

Method for implementing large multiplexers with FPGA lookup tables

Abstract: A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA architecture. In one situation, a large multiplexer is implemented in two stages. The first stage implements wide AND functions of each of the input signals using lookup tables and carry logic. In a second stage, the resulting decoded input signals are combined in a wide OR gate again formed from lookup tables and a carry chain. In another situation, the multiplexer is implemented as a tree structure using lookup tables that implement 2:1 multiplexers in combination with other 2:1 multiplexers provided by configurable logic blocks of the FPGA.

A novel predictable segmented FPGA routing architecture

Abstract: In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.

Circuit for selecting a bit in a look-up table

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Combined waveform and data entry apparatus and method for facilitating fast behavioral verification of digital hardware designs

Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.

System and method of computation in a programmable logic device using virtual instructions

Abstract: An FPGA configuration provides a virtual instruction. In a generic computation, the output pattern of a first instruction is compared to the input pattern of a second instruction. If the input and output patterns of the first and second instructions do not match, then a pattern manipulation instruction is inserted between the first and second instructions. At this point, the input and output patterns of the first and second instructions should match and the computation task can be completed. The method of providing virtual instructions is applicable to any FPGA. In a standard FPGA, the data stored in the storage elements of the FPGA, such as flip-flops, is retained for the next configuration of the FPGA. In this manner, successive configurations can communicate data using the patterns of the storage elements, thereby allowing standard FPGAs to implement virtual instructions. Alternatively, a standard FPGA could write out data to an external memory using a predetermined pattern of addresses. In a subsequent configuration of the FPGA, the device could read data back from this pattern of addresses in the external memory. This embodiment allows various patterns of addresses, corresponding to data, to be used in any appropriate subsequent configuration of the FPGA. In this manner, the plurality of memory planes, previously provided on the dynamically reconfigurable FPGA, can be implemented off-chip.